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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-17 13:16:07 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-24 14:58:47 +0100 |
| commit | 91a358fdfb3b116a6ea72a38d5c217caad1d45b5 (patch) | |
| tree | af331bb0fd601f2b136fd33005640c7f8425d5ca /target/arm | |
| parent | e51896b3866ffb74df5aaa3b33c35e7113e5c6b9 (diff) | |
| download | qemu-91a358fdfb3b116a6ea72a38d5c217caad1d45b5.zip qemu-91a358fdfb3b116a6ea72a38d5c217caad1d45b5.tar.gz qemu-91a358fdfb3b116a6ea72a38d5c217caad1d45b5.tar.bz2 | |
target/arm: Implement MVE VSUB, VMUL (scalar)
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-24-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper-mve.h | 8 | ||||
| -rw-r--r-- | target/arm/mve.decode | 2 | ||||
| -rw-r--r-- | target/arm/mve_helper.c | 2 | ||||
| -rw-r--r-- | target/arm/translate-mve.c | 2 |
4 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 16b974a..912505d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -149,6 +149,14 @@ DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vsub_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vsub_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 0ee7a72..af5fba7 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -161,3 +161,5 @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_no # Scalar operations VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar +VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 6b8cead..33755bc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -512,6 +512,8 @@ DO_2OP_U(vhsubu, do_vhsub_u) DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) +DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) +DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) /* * Multiply add long dual accumulate ops. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 388848b..3c059ad 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -427,6 +427,8 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, } DO_2OP_SCALAR(VADD_scalar, vadd_scalar) +DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) +DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) |