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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-07-19 09:49:00 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-10-21 21:29:25 +0300 |
| commit | 19b7bec4a37b081ed326293148fd793f04896b59 (patch) | |
| tree | 97058af758983de0f2df5190105d1f1b637d4229 /target-xtensa | |
| parent | 5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6 (diff) | |
| download | qemu-19b7bec4a37b081ed326293148fd793f04896b59.zip qemu-19b7bec4a37b081ed326293148fd793f04896b59.tar.gz qemu-19b7bec4a37b081ed326293148fd793f04896b59.tar.bz2 | |
target-xtensa: implement S32NB
S32NB provides the same functionality as S32I with two exceptions.
First, when its operation leaves the processor, the external transaction
is marked Non-Bufferable. Second, it may not be used to write to
Instruction RAM.
In QEMU S32NB is equivalent to S32I.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa')
| -rw-r--r-- | target-xtensa/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index be5eb25..aa0c527 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1965,6 +1965,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } break; + case 5: /*S32N*/ + if (gen_window_check2(dc, RRI4_S, RRI4_T)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); + tcg_temp_free(addr); + } + break; + default: RESERVED(); break; |