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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-07-12 02:10:17 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-10-21 21:29:25 +0300 |
| commit | 5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6 (patch) | |
| tree | 905608e83c2d6180f862d13cec353016691725b0 /target-xtensa | |
| parent | 68931a4082812f56657b39168e815c48f0ab0a8c (diff) | |
| download | qemu-5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6.zip qemu-5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6.tar.gz qemu-5eeb40c5b1f00c4ee4fcf2f33087697d7ba6f5f6.tar.bz2 | |
target-xtensa: implement depbits instruction
This option provides an instruction for depositing a bit field from the
least significant position of one register to an arbitrary position in
another register.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target-xtensa')
| -rw-r--r-- | target-xtensa/cpu.h | 1 | ||||
| -rw-r--r-- | target-xtensa/overlay_tool.h | 5 | ||||
| -rw-r--r-- | target-xtensa/translate.c | 20 |
3 files changed, 26 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 006bcb7..15ce010 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -64,6 +64,7 @@ enum { XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, XTENSA_OPTION_ATOMCTL, + XTENSA_OPTION_DEPBITS, /* Interrupts and exceptions */ XTENSA_OPTION_EXCEPTION, diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index eda03aa..e8a7fda 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -30,6 +30,10 @@ { .targno = (no), .type = (typ), .group = (grp), .size = (sz) }, #define XTREG_END { .targno = -1 }, +#ifndef XCHAL_HAVE_DEPBITS +#define XCHAL_HAVE_DEPBITS 0 +#endif + #ifndef XCHAL_HAVE_DIV32 #define XCHAL_HAVE_DIV32 0 #endif @@ -69,6 +73,7 @@ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \ XTENSA_OPTION_ATOMCTL) | \ + XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ /* Interrupts and exceptions */ \ XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1349d2f..be5eb25 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1972,6 +1972,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 10: /*FP0*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); switch (OP2) { case 0: /*ADD.Sf*/ @@ -2106,6 +2116,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 11: /*FP1*/ + /*DEPBITS*/ + if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { + if (!gen_window_check2(dc, RRR_S, RRR_T)) { + break; + } + tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], + OP2 + 16, RRR_R + 1); + break; + } + HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); #define gen_compare(rel, br, a, b) \ |