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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:08 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | 27c22b2de08f71500df581563cc9d22638a14b4d (patch) | |
| tree | 97076925e1db576b9b4c7fde3ca413964d79f3cc /include | |
| parent | cdd58c70fbcb7276d3df656941278e4395ecce14 (diff) | |
| download | qemu-27c22b2de08f71500df581563cc9d22638a14b4d.zip qemu-27c22b2de08f71500df581563cc9d22638a14b4d.tar.gz qemu-27c22b2de08f71500df581563cc9d22638a14b4d.tar.bz2 | |
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 245c82d..f34a6b3 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -74,6 +74,7 @@ typedef struct MicrochipIcicleKitState { TYPE_MICROCHIP_ICICLE_KIT_MACHINE) enum { + MICROCHIP_PFSOC_RSVD0, MICROCHIP_PFSOC_DEBUG, MICROCHIP_PFSOC_E51_DTIM, MICROCHIP_PFSOC_BUSERR_UNIT0, |