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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-11-17 22:55:18 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | 592f0a9429b924bc7eec0aee60afa391f7ca96b2 (patch) | |
| tree | 8f45f7eb4fb33777a84712a1b33ddc0ddb4a9c2f /include/hw/riscv | |
| parent | 8d32e374a805976c622ed58073015eaf2e6859dc (diff) | |
| download | qemu-592f0a9429b924bc7eec0aee60afa391f7ca96b2.zip qemu-592f0a9429b924bc7eec0aee60afa391f7ca96b2.tar.gz qemu-592f0a9429b924bc7eec0aee60afa391f7ca96b2.tar.bz2 | |
hw/{misc, riscv}: pfsoc: add system controller as unimplemented
The system controller on PolarFire SoC is access via a mailbox. The
control registers for this mailbox lie in the "IOSCB" region & the
interrupt is cleared via write to the "SYSREG" region. It also has a
QSPI controller, usually connected to a flash chip, that is used for
storing FPGA bitstreams and used for In-Application Programming (IAP).
Linux has an implementation of the system controller, through which the
hwrng is accessed, leading to load/store access faults.
Add the QSPI as unimplemented and a very basic (effectively
unimplemented) version of the system controller's mailbox. Rather than
purely marking the regions as unimplemented, service the mailbox
requests by reporting failures and raising the interrupt so a guest can
better handle the lack of support.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221117225518.4102575-4-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 7e7950d..69a686b 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -147,6 +147,7 @@ enum { MICROCHIP_PFSOC_MMUART2_IRQ = 92, MICROCHIP_PFSOC_MMUART3_IRQ = 93, MICROCHIP_PFSOC_MMUART4_IRQ = 94, + MICROCHIP_PFSOC_MAILBOX_IRQ = 96, }; #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 |