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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-20 14:25:26 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-03-03 13:14:50 +1000 |
| commit | 0631aaae31cccf5ae61e8c67c198e064bfaafc66 (patch) | |
| tree | ec2a60aac36861b8aa015c4e68bfdeb7803e4f3d /include/hw/riscv | |
| parent | c65bc383edc7aa7c12afcdad3be30521b3280203 (diff) | |
| download | qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.zip qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.tar.gz qemu-0631aaae31cccf5ae61e8c67c198e064bfaafc66.tar.bz2 | |
hw/riscv: virt: Increase maximum number of allowed CPUs
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/virt.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index d248d0d..78b058e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "qom/object.h" -#define VIRT_CPUS_MAX_BITS 3 +#define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) #define VIRT_SOCKETS_MAX_BITS 2 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) |