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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-12 19:13:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-21 16:29:27 +0100 |
| commit | e1be0a576ba4836e772d717fcc8d3c79e560179b (patch) | |
| tree | 5d750d5c56fe76abe8b29e2faa80f1643088bfa9 /include/hw/intc | |
| parent | 028b0da424ba85049557c61f9f0a8a6698352b41 (diff) | |
| download | qemu-e1be0a576ba4836e772d717fcc8d3c79e560179b.zip qemu-e1be0a576ba4836e772d717fcc8d3c79e560179b.tar.gz qemu-e1be0a576ba4836e772d717fcc8d3c79e560179b.tar.bz2 | |
nvic: Implement NVIC_ITNS<n> registers
For v8M, the NVIC has a new set of registers per interrupt,
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
or Non-secure state. Implement the register read/write code for
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
accesses to fields corresponding to interrupts which are
configured to target secure state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/intc')
| -rw-r--r-- | include/hw/intc/armv7m_nvic.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index e96e488..ac7997c 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -58,6 +58,9 @@ typedef struct NVICState { /* The PRIGROUP field in AIRCR is banked */ uint32_t prigroup[M_REG_NUM_BANKS]; + /* v8M NVIC_ITNS state (stored as a bool per bit) */ + bool itns[NVIC_MAX_VECTORS]; + /* The following fields are all cached state that can be recalculated * from the vectors[] and sec_vectors[] arrays and the prigroup field: * - vectpending |