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author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-04 15:21:53 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-04 15:21:53 +0100 |
commit | d2db1de6ff15aad4c8898a416c6d8f2d93ff0282 (patch) | |
tree | f8a4e8e924738ad58863c4759bf50b4b568ab1f3 /include/hw/intc | |
parent | 15b3f556bab4f961bf92141eb8521c8da3df5eb2 (diff) | |
download | qemu-d2db1de6ff15aad4c8898a416c6d8f2d93ff0282.zip qemu-d2db1de6ff15aad4c8898a416c6d8f2d93ff0282.tar.gz qemu-d2db1de6ff15aad4c8898a416c6d8f2d93ff0282.tar.bz2 |
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
The armv7m_nvic.h header file was accidentally placed in
include/hw/arm; move it to include/hw/intc to match where
its corresponding .c file lives.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1501692241-23310-15-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/intc')
-rw-r--r-- | include/hw/intc/armv7m_nvic.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h new file mode 100644 index 0000000..1d145fb --- /dev/null +++ b/include/hw/intc/armv7m_nvic.h @@ -0,0 +1,62 @@ +/* + * ARMv7M NVIC object + * + * Copyright (c) 2017 Linaro Ltd + * Written by Peter Maydell <peter.maydell@linaro.org> + * + * This code is licensed under the GPL version 2 or later. + */ + +#ifndef HW_ARM_ARMV7M_NVIC_H +#define HW_ARM_ARMV7M_NVIC_H + +#include "target/arm/cpu.h" +#include "hw/sysbus.h" +#include "hw/timer/armv7m_systick.h" + +#define TYPE_NVIC "armv7m_nvic" + +#define NVIC(obj) \ + OBJECT_CHECK(NVICState, (obj), TYPE_NVIC) + +/* Highest permitted number of exceptions (architectural limit) */ +#define NVIC_MAX_VECTORS 512 + +typedef struct VecInfo { + /* Exception priorities can range from -3 to 255; only the unmodifiable + * priority values for RESET, NMI and HardFault can be negative. + */ + int16_t prio; + uint8_t enabled; + uint8_t pending; + uint8_t active; + uint8_t level; /* exceptions <=15 never set level */ +} VecInfo; + +typedef struct NVICState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + ARMCPU *cpu; + + VecInfo vectors[NVIC_MAX_VECTORS]; + uint32_t prigroup; + + /* vectpending and exception_prio are both cached state that can + * be recalculated from the vectors[] array and the prigroup field. + */ + unsigned int vectpending; /* highest prio pending enabled exception */ + int exception_prio; /* group prio of the highest prio active exception */ + + MemoryRegion sysregmem; + MemoryRegion container; + + uint32_t num_irq; + qemu_irq excpout; + qemu_irq sysresetreq; + + SysTickState systick; +} NVICState; + +#endif |