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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-12 19:13:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-21 16:28:23 +0100 |
| commit | 50f11062d4c896408731d6a286bcd116d1e08465 (patch) | |
| tree | 117767ff2c9ceaa8c9a7749c2b486c3db5d95c05 /include/hw/intc | |
| parent | 9ee660e7c138595224b65ddc1c5712549f0a278c (diff) | |
| download | qemu-50f11062d4c896408731d6a286bcd116d1e08465.zip qemu-50f11062d4c896408731d6a286bcd116d1e08465.tar.gz qemu-50f11062d4c896408731d6a286bcd116d1e08465.tar.bz2 | |
target/arm: Implement MSR/MRS access to NS banked registers
In v8M the MSR and MRS instructions have extra register value
encodings to allow secure code to access the non-secure banked
version of various special registers.
(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
we don't currently implement the stack limit registers at all.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/intc')
0 files changed, 0 insertions, 0 deletions