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| author | Luc Michel <luc.michel@greensocs.com> | 2018-08-14 17:17:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-14 17:17:19 +0100 |
| commit | 3bb0b03897abb634231366ce4e6651b56f16aa26 (patch) | |
| tree | 3add5315c37b2029e5dae5b33783e4f8b27ca40c /include/hw/intc | |
| parent | 67ce697ac84bd7f44348830df43f05195d5987e6 (diff) | |
| download | qemu-3bb0b03897abb634231366ce4e6651b56f16aa26.zip qemu-3bb0b03897abb634231366ce4e6651b56f16aa26.tar.gz qemu-3bb0b03897abb634231366ce4e6651b56f16aa26.tar.bz2 | |
intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-3-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/intc')
0 files changed, 0 insertions, 0 deletions