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authorPeter Maydell <peter.maydell@linaro.org>2017-09-12 19:13:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-09-21 16:29:27 +0100
commit3b2e934463121f06d04e4d17658a9a7cdc3717b0 (patch)
tree41c8a79405ca0503de405a2bfc79625dd939e25d /include/hw/intc
parent5255fcf8e47acd059e2f0d414841c40231c1bd22 (diff)
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nvic: Implement AIRCR changes for v8M
The Application Interrupt and Reset Control Register has some changes for v8M: * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have real state if the security extension is implemented and otherwise are constant * the PRIGROUP field is banked between security states * non-secure code can be blocked from using the SYSRESET bit to reset the system if SYSRESETREQS is set Implement the new state and the changes to register read and write. For the moment we ignore the effects of the secure PRIGROUP. We will implement the effects of PRIS and BFHFNMIS later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/intc')
-rw-r--r--include/hw/intc/armv7m_nvic.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 329774e8..e96e488 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -55,7 +55,8 @@ typedef struct NVICState {
* Entries in sec_vectors[] for non-banked exception numbers are unused.
*/
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
- uint32_t prigroup;
+ /* The PRIGROUP field in AIRCR is banked */
+ uint32_t prigroup[M_REG_NUM_BANKS];
/* The following fields are all cached state that can be recalculated
* from the vectors[] and sec_vectors[] arrays and the prigroup field: