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| author | Helge Deller <deller@gmx.de> | 2023-10-16 14:43:18 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | f3618f59f3559eae69c34e0fe621685614b4350d (patch) | |
| tree | 31d98f6c9caf73a3a5057bc4d5c606d45f811006 /hw | |
| parent | f13bf343ccdb7df14233133f42670e1b16bb6b20 (diff) | |
| download | qemu-f3618f59f3559eae69c34e0fe621685614b4350d.zip qemu-f3618f59f3559eae69c34e0fe621685614b4350d.tar.gz qemu-f3618f59f3559eae69c34e0fe621685614b4350d.tar.bz2 | |
target/hppa: sar register allows only 5 bits on 32-bit CPU
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions