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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
| commit | a007b1f85813ef6450ad3e761e46c189e3f40e04 (patch) | |
| tree | 4aaba13964ee90785426e10c067e95a015d9fb48 /hw | |
| parent | 9ff9dd3c875956523bb4c19ca712e5d05aab3c65 (diff) | |
| download | qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.zip qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.tar.gz qemu-a007b1f85813ef6450ad3e761e46c189e3f40e04.tar.bz2 | |
hw/arm/virt: Wire up secure timer interrupt
Wire up the secure timer interrupt. Since we've defined
that the plain old physical timer is the NS timer, we can
drop the now-out-of-date comment about QEMU not having TZ.
Use a data-driven loop to wire up the timer interrupts, since
we now have four of them and the code is the same for each.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1437047249-2357-4-git-send-email-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/virt.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 94694d6..d5a8417 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -391,20 +391,22 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) for (i = 0; i < smp_cpus; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; - /* physical timer; we wire it up to the non-secure timer's ID, - * since a real A15 always has TrustZone but QEMU doesn't. + int irq; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. */ - qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_NS_EL1_IRQ)); - /* virtual timer */ - qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_VIRT_IRQ)); - /* Hypervisor timer. */ - qdev_connect_gpio_out(cpudev, 2, - qdev_get_gpio_in(gicdev, - ppibase + ARCH_TIMER_NS_EL2_IRQ)); + const int timer_irq[] = { + [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq])); + } sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, |