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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-08-13 11:26:22 +0100 |
| commit | 9ff9dd3c875956523bb4c19ca712e5d05aab3c65 (patch) | |
| tree | ba0b94ea33a9cf9a88468518c33c9cc106ba8612 /hw | |
| parent | b4d3978c2fdf944e428a46d2850dbd950b6fbe78 (diff) | |
| download | qemu-9ff9dd3c875956523bb4c19ca712e5d05aab3c65.zip qemu-9ff9dd3c875956523bb4c19ca712e5d05aab3c65.tar.gz qemu-9ff9dd3c875956523bb4c19ca712e5d05aab3c65.tar.bz2 | |
target-arm: Add AArch32 banked register access to secure physical timer
If EL3 is AArch32, then the secure physical timer is accessed via
banking of the registers used for the non-secure physical timer.
Implement this banking.
Note that the access controls for the AArch32 banked registers
remain the same as the physical-timer checks; they are not the
same as the controls on the AArch64 secure timer registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1437047249-2357-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions