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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-04-24 23:49:17 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-22 19:43:29 +0200 |
| commit | 6ddeb0ec8c29d51be49d5336c6d6508972b6d49c (patch) | |
| tree | ffd35da99e2abaedfb8dd57c52e9653416006b31 /hw | |
| parent | 2613747a794c4de8cd04e4a24001765220e91f1b (diff) | |
| download | qemu-6ddeb0ec8c29d51be49d5336c6d6508972b6d49c.zip qemu-6ddeb0ec8c29d51be49d5336c6d6508972b6d49c.tar.gz qemu-6ddeb0ec8c29d51be49d5336c6d6508972b6d49c.tar.bz2 | |
i386/cpu: Introduce bitmap to cache available CPU topology levels
Currently, QEMU checks the specify number of topology domains to detect
if there's extended topology levels (e.g., checking nr_dies).
With this bitmap, the extended CPU topology (the levels other than SMT,
core and package) could be easier to detect without touching the
topology details.
This is also in preparation for the follow-up to decouple CPUID[0x1F]
subleaf with specific topology level.
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20240424154929.1487382-10-zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i386/x86-common.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 67b03c9..7d4f9b2 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,7 +271,10 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); - env->nr_dies = ms->smp.dies; + if (ms->smp.dies > 1) { + env->nr_dies = ms->smp.dies; + set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); + } /* * If APIC ID is not set, |