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authorAlistair Francis <alistair.francis@wdc.com>2021-08-30 15:35:02 +1000
committerAlistair Francis <alistair.francis@wdc.com>2021-09-21 07:56:49 +1000
commitf436ecc3156dea7edce97e7c247e3667203f5c8b (patch)
tree1ca775b95bfaa3f19cb76a7cff031ac9aa05c4e0 /hw/riscv/microchip_pfsoc.c
parente5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa (diff)
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hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/microchip_pfsoc.c')
-rw-r--r--hw/riscv/microchip_pfsoc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index eb8e79e..eef55f6 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -274,7 +274,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
/* PLIC */
s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
- plic_hart_config, 0,
+ plic_hart_config, ms->smp.cpus, 0,
MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,