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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:38 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | ffffd954ba168d5b6812d25b8cf49d160874f241 (patch) | |
| tree | 4c19a0e84694c102d71c2d4dea4f257e97f030c5 /hw/misc/sifive_u_prci.c | |
| parent | c00226e1f0620fda90c985631b31afe2a87f7e97 (diff) | |
| download | qemu-ffffd954ba168d5b6812d25b8cf49d160874f241.zip qemu-ffffd954ba168d5b6812d25b8cf49d160874f241.tar.gz qemu-ffffd954ba168d5b6812d25b8cf49d160874f241.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_d
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions