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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:37 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | c00226e1f0620fda90c985631b31afe2a87f7e97 (patch) | |
| tree | 87892fd8d8b423f8997945c28928ac2f8c492b01 /hw/misc/sifive_u_prci.c | |
| parent | 4c759943ec23bca891ad25fb2a9988f1b78f9e7d (diff) | |
| download | qemu-c00226e1f0620fda90c985631b31afe2a87f7e97.zip qemu-c00226e1f0620fda90c985631b31afe2a87f7e97.tar.gz qemu-c00226e1f0620fda90c985631b31afe2a87f7e97.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_c
Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions