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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:44 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | e17801e1708da60371550af5a67e14c7d8db4eae (patch) | |
| tree | 8050639d0e2993e52fca34021e3637c283e51fcd /hw/misc/sifive_u_prci.c | |
| parent | f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1 (diff) | |
| download | qemu-e17801e1708da60371550af5a67e14c7d8db4eae.zip qemu-e17801e1708da60371550af5a67e14c7d8db4eae.tar.gz qemu-e17801e1708da60371550af5a67e14c7d8db4eae.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_u
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions