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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:43 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1 (patch) | |
| tree | f16bb21e51cd3ffe092dbc1420e6f6a1eaad0e09 /hw/misc/sifive_u_prci.c | |
| parent | 1a36e23a62283ecca1b56a983cfce67e4ec84ee7 (diff) | |
| download | qemu-f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1.zip qemu-f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1.tar.gz qemu-f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_s
Create a new "s" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
replaced with riscv_has_ext(env, RVS).
Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions