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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:36 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 4c759943ec23bca891ad25fb2a9988f1b78f9e7d (patch) | |
| tree | 0d35cff3c218c465bcaa1dfe4278a9064922aa13 /hw/misc/sifive_u_prci.c | |
| parent | b3df64c89bd18b81e7689b8e26ef940e9a7ff078 (diff) | |
| download | qemu-4c759943ec23bca891ad25fb2a9988f1b78f9e7d.zip qemu-4c759943ec23bca891ad25fb2a9988f1b78f9e7d.tar.gz qemu-4c759943ec23bca891ad25fb2a9988f1b78f9e7d.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_a
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions