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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:40 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 74828eabf2c301ff93fee297519d25e0f1804b2a (patch) | |
| tree | d60b5a780193c1f657dea6849d872cc81e06ea6b /hw/misc/sifive_u_prci.c | |
| parent | 4b33598fbe8cd899a08e7ac1cff9b9cb1e8477e9 (diff) | |
| download | qemu-74828eabf2c301ff93fee297519d25e0f1804b2a.zip qemu-74828eabf2c301ff93fee297519d25e0f1804b2a.tar.gz qemu-74828eabf2c301ff93fee297519d25e0f1804b2a.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_i
Create a new "i" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
replaced with riscv_has_ext(env, RVI).
Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions