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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:48 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 7295b18606602c6b0b841a0f089db7f01b6c7ec1 (patch) | |
| tree | e62619fe8dfd74a2540b5258a4c31a94fa51db60 /hw/misc/sifive_u_prci.c | |
| parent | 3e7674fd1ab1f04b811629123190b80fea15e41d (diff) | |
| download | qemu-7295b18606602c6b0b841a0f089db7f01b6c7ec1.zip qemu-7295b18606602c6b0b841a0f089db7f01b6c7ec1.tar.gz qemu-7295b18606602c6b0b841a0f089db7f01b6c7ec1.tar.bz2 | |
target/riscv: remove riscv_cpu_sync_misa_cfg()
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an existing MISA bit
(cfg.ext_g will be handled shortly). The function is now a no-op, simply
copying the existing values of misa_ext* back to misa_ext*.
Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions