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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:47 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 3e7674fd1ab1f04b811629123190b80fea15e41d (patch) | |
| tree | acdede62d3bf3f8769e5537672efce2c3fa6ca30 /hw/misc/sifive_u_prci.c | |
| parent | 64f4b541c52d3ea581e9123b5bab8b915323e76d (diff) | |
| download | qemu-3e7674fd1ab1f04b811629123190b80fea15e41d.zip qemu-3e7674fd1ab1f04b811629123190b80fea15e41d.tar.gz qemu-3e7674fd1ab1f04b811629123190b80fea15e41d.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_v
Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions