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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:46 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 64f4b541c52d3ea581e9123b5bab8b915323e76d (patch) | |
| tree | 9c1d6be9c306f66dfbbdd123bb8e2e502c0262b8 /hw/misc/sifive_u_prci.c | |
| parent | b5c042e8a0300989b7e9ce0d24b6535c77439d3e (diff) | |
| download | qemu-64f4b541c52d3ea581e9123b5bab8b915323e76d.zip qemu-64f4b541c52d3ea581e9123b5bab8b915323e76d.tar.gz qemu-64f4b541c52d3ea581e9123b5bab8b915323e76d.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_j
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions