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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:04 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | a937b302831f12094437cdbdfc859bff9f093525 (patch) | |
| tree | 1e261b3c39df4066f0da2f61ffb2da9cee3df64c /hw/misc/Kconfig | |
| parent | 933f73f13e5ceb9357e9c9d51ce39c43aa1d534f (diff) | |
| download | qemu-a937b302831f12094437cdbdfc859bff9f093525.zip qemu-a937b302831f12094437cdbdfc859bff9f093525.tar.gz qemu-a937b302831f12094437cdbdfc859bff9f093525.tar.bz2 | |
hw/misc: Add Microchip PolarFire SoC IOSCB module support
This creates a model for PolarFire SoC IOSCB [1] module. It actually
contains lots of sub-modules like various PLLs to control different
peripherals. Only the mininum capabilities are emulated to make the
HSS DDR memory initialization codes happy. Lots of sub-modules are
created as an unimplemented devices.
[1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/Kconfig')
| -rw-r--r-- | hw/misc/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 32ab718..4ff01ec 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -142,6 +142,9 @@ config AVR_POWER config MCHP_PFSOC_DMC bool +config MCHP_PFSOC_IOSCB + bool + config SIFIVE_TEST bool |