diff options
author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-18 12:43:40 +0000 |
---|---|---|
committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-18 12:43:40 +0000 |
commit | 39d51eb8bcc603c02342d8f5e1f7a569e5f17e06 (patch) | |
tree | 3036073718e3ba76bc3143261d6caee489d03538 /hw/mips_timer.c | |
parent | 36f696517b1723d627b79aa924bac7c678de01b0 (diff) | |
download | qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.zip qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.tar.gz qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.tar.bz2 |
Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/mips_timer.c')
-rw-r--r-- | hw/mips_timer.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/mips_timer.c b/hw/mips_timer.c index bc83036..055ee5b 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -28,6 +28,9 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count, uint64_t now, next; uint32_t tmp; + if (env->CP0_Cause & (1 << CP0Ca_DC)) + return; + tmp = count; if (count == compare) tmp++; @@ -57,6 +60,8 @@ void cpu_mips_store_count (CPUState *env, uint32_t value) void cpu_mips_store_compare (CPUState *env, uint32_t value) { cpu_mips_update_count(env, cpu_mips_get_count(env), value); + if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) + env->CP0_Cause &= ~(1 << CP0Ca_TI); cpu_mips_irq_request(env, 7, 0); } @@ -71,6 +76,8 @@ static void mips_timer_cb (void *opaque) } #endif cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); + if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) + env->CP0_Cause |= 1 << CP0Ca_TI; cpu_mips_irq_request(env, 7, 1); } |