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authorRichard Henderson <richard.henderson@linaro.org>2023-09-13 17:56:21 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-10-04 11:03:54 -0700
commit7857ee114c6518165653d3ba87f24a1815c26f6f (patch)
treecef853de0a34cd94e09ec6a97a3303984133fea3 /accel/tcg
parent06ddecff244a7fbb2c98352cdfed44fea66608bc (diff)
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tcg: Remove TCGContext.tlb_fast_offset
Now that there is no padding between CPUNegativeOffsetState and CPUArchState, this value is constant across all targets. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg')
-rw-r--r--accel/tcg/translate-all.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 6fac5b7..83e07b8 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -344,8 +344,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->page_bits = TARGET_PAGE_BITS;
tcg_ctx->page_mask = TARGET_PAGE_MASK;
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
- tcg_ctx->tlb_fast_offset = (int)offsetof(ArchCPU, parent_obj.neg.tlb.f)
- - (int)offsetof(ArchCPU, env);
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
#ifdef TCG_GUEST_DEFAULT_MO