diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2020-01-07 10:31:07 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-07 10:31:07 +0000 |
commit | cdbc5c51c8755e4e9ce964fc92ba755e1c71a914 (patch) | |
tree | fb98ec8471eae30d891d55026ba56ac7d5010533 | |
parent | c4d1069c2563f70a5271af6e9e000add64e593be (diff) | |
parent | a153a3f73d8e028be996f1602fa99c7f3f53348c (diff) | |
download | qemu-cdbc5c51c8755e4e9ce964fc92ba755e1c71a914.zip qemu-cdbc5c51c8755e4e9ce964fc92ba755e1c71a914.tar.gz qemu-cdbc5c51c8755e4e9ce964fc92ba755e1c71a914.tar.bz2 |
Merge remote-tracking branch 'remotes/xtensa/tags/20200106-xtensa' into staging
target/xtensa improvements for v5.0:
- fix ps.ring use in MPU configs;
- use MPU background map from the configuration overlay.
# gpg: Signature made Mon 06 Jan 2020 20:00:33 GMT
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20200106-xtensa:
target/xtensa: use MPU background map from core configuration
target/xtensa: import xtensa/config/core-isa.h
target/xtensa: fix ps.ring use in MPU configs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/xtensa/cpu.h | 10 | ||||
-rwxr-xr-x | target/xtensa/import_core.sh | 6 | ||||
-rw-r--r-- | target/xtensa/overlay_tool.h | 15 | ||||
-rw-r--r-- | target/xtensa/translate.c | 3 |
4 files changed, 27 insertions, 7 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b363ffc..75e65df 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -645,7 +645,9 @@ static inline int xtensa_get_cintlevel(const CPUXtensaState *env) static inline int xtensa_get_ring(const CPUXtensaState *env) { - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + if (xtensa_option_bits_enabled(env->config, + XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | + XTENSA_OPTION_BIT(XTENSA_OPTION_MPU))) { return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; } else { return 0; @@ -654,8 +656,10 @@ static inline int xtensa_get_ring(const CPUXtensaState *env) static inline int xtensa_get_cring(const CPUXtensaState *env) { - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && - (env->sregs[PS] & PS_EXCM) == 0) { + if (xtensa_option_bits_enabled(env->config, + XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | + XTENSA_OPTION_BIT(XTENSA_OPTION_MPU)) && + (env->sregs[PS] & PS_EXCM) == 0) { return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; } else { return 0; diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index e4a2e39..8f844cf 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -19,8 +19,9 @@ exit [ $# -ge 3 ] && FREQ="$3" mkdir -p "$TARGET" -tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \ - --xform='s/core/core-isa/' config/core.h +tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \ + xtensa/config/core-isa.h \ + xtensa/config/core-matmap.h tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c # @@ -44,6 +45,7 @@ cat <<EOF > "${TARGET}.c" #include "qemu/host-utils.h" #include "core-$NAME/core-isa.h" +#include "core-$NAME/core-matmap.h" #include "overlay_tool.h" #define xtensa_modules xtensa_modules_$NAME diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index f0cc33a..cab5320 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -373,15 +373,28 @@ #elif XCHAL_HAVE_MPU #ifndef XTENSA_MPU_BG_MAP +#ifdef XCHAL_MPU_BACKGROUND_MAP +#define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \ + { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), }, + +#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ + XCHAL_MPU_BACKGROUND_MAP(0) \ +} + +#define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES +#else #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ { .vaddr = 0, .attr = 0x00006700, }, \ } + +#define XTENSA_MPU_BG_MAP_ENTRIES 1 +#endif #endif #define TLB_SECTION \ .mpu_align = XCHAL_MPU_ALIGN, \ .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \ - .n_mpu_bg_segments = 1, \ + .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \ .mpu_bg = XTENSA_MPU_BG_MAP #ifndef XCHAL_SYSROM0_PADDR diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a99f529..e6d9107 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2713,7 +2713,8 @@ static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | PS_UM | PS_EXCM | PS_INTLEVEL; - if (option_enabled(dc, XTENSA_OPTION_MMU)) { + if (option_enabled(dc, XTENSA_OPTION_MMU) || + option_enabled(dc, XTENSA_OPTION_MPU)) { mask |= PS_RING; } tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask); |