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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-12-07 22:27:23 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-01-06 11:46:16 -0800 |
| commit | a153a3f73d8e028be996f1602fa99c7f3f53348c (patch) | |
| tree | d93e93cab5f623126f7c71122e356d1e541ca738 | |
| parent | ca3c979d6be82e88bd19ade3f6e4c9c2bc4887ea (diff) | |
| download | qemu-a153a3f73d8e028be996f1602fa99c7f3f53348c.zip qemu-a153a3f73d8e028be996f1602fa99c7f3f53348c.tar.gz qemu-a153a3f73d8e028be996f1602fa99c7f3f53348c.tar.bz2 | |
target/xtensa: use MPU background map from core configuration
Configuration overlay may define MPU background map. Import
core-matmap.h from the overlay and use XCHAL_MPU_BACKGROUND_MAP macro
if it's defined.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rwxr-xr-x | target/xtensa/import_core.sh | 4 | ||||
| -rw-r--r-- | target/xtensa/overlay_tool.h | 15 |
2 files changed, 17 insertions, 2 deletions
diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index 97c3219..8f844cf 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -20,7 +20,8 @@ exit [ $# -ge 3 ] && FREQ="$3" mkdir -p "$TARGET" tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \ - xtensa/config/core-isa.h + xtensa/config/core-isa.h \ + xtensa/config/core-matmap.h tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c # @@ -44,6 +45,7 @@ cat <<EOF > "${TARGET}.c" #include "qemu/host-utils.h" #include "core-$NAME/core-isa.h" +#include "core-$NAME/core-matmap.h" #include "overlay_tool.h" #define xtensa_modules xtensa_modules_$NAME diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index f0cc33a..cab5320 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -373,15 +373,28 @@ #elif XCHAL_HAVE_MPU #ifndef XTENSA_MPU_BG_MAP +#ifdef XCHAL_MPU_BACKGROUND_MAP +#define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \ + { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), }, + +#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ + XCHAL_MPU_BACKGROUND_MAP(0) \ +} + +#define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES +#else #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ { .vaddr = 0, .attr = 0x00006700, }, \ } + +#define XTENSA_MPU_BG_MAP_ENTRIES 1 +#endif #endif #define TLB_SECTION \ .mpu_align = XCHAL_MPU_ALIGN, \ .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \ - .n_mpu_bg_segments = 1, \ + .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \ .mpu_bg = XTENSA_MPU_BG_MAP #ifndef XCHAL_SYSROM0_PADDR |