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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-01-22 13:11:03 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
commit | bd2c82283d21e3400d7d89676a221935904c2fe6 (patch) | |
tree | 40cf0aed58ab41ba89b199ea7844342ad27f5b04 | |
parent | 7aa4d519cba610876abac027a5812af87c834d22 (diff) | |
download | qemu-bd2c82283d21e3400d7d89676a221935904c2fe6.zip qemu-bd2c82283d21e3400d7d89676a221935904c2fe6.tar.gz qemu-bd2c82283d21e3400d7d89676a221935904c2fe6.tar.bz2 |
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
Calculate the maximum vector size possible, 'max_sz', which is the size
in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
s->lmul = 3).
'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
which is clearer than doing 'scale = lmul - 3' and then using '-scale'
in the shift right.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index d743675..b4663b6 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1160,12 +1160,12 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true) /* * MAXSZ returns the maximum vector size can be operated in bytes, * which is used in GVEC IR when vl_eq_vlmax flag is set to true - * to accerlate vector operation. + * to accelerate vector operation. */ static inline uint32_t MAXSZ(DisasContext *s) { - int scale = s->lmul - 3; - return s->cfg_ptr->vlen >> -scale; + int max_sz = s->cfg_ptr->vlenb * 8; + return max_sz >> (3 - s->lmul); } static bool opivv_check(DisasContext *s, arg_rmrr *a) |