diff options
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-01-22 13:11:02 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | 7aa4d519cba610876abac027a5812af87c834d22 (patch) | |
| tree | 44ef49a8b8187233ecfb4b8aceec2b2cc91a329e | |
| parent | 58bc9063ec06c7b1812ae787b748f05838cae193 (diff) | |
| download | qemu-7aa4d519cba610876abac027a5812af87c834d22.zip qemu-7aa4d519cba610876abac027a5812af87c834d22.tar.gz qemu-7aa4d519cba610876abac027a5812af87c834d22.tar.bz2 | |
target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
to use vlenb.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/vector_helper.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 908e69d..8ee7717 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -45,9 +45,16 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, xlen - 1 - R_VTYPE_RESERVED_SHIFT); if (lmul & 4) { - /* Fractional LMUL - check LMUL * VLEN >= SEW */ + /* + * Fractional LMUL, check: + * + * VLEN * LMUL >= SEW + * VLEN >> (8 - lmul) >= sew + * (vlenb << 3) >> (8 - lmul) >= sew + * vlenb >> (8 - 3 - lmul) >= sew + */ if (lmul == 4 || - cpu->cfg.vlen >> (8 - lmul) < sew) { + cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) { vill = true; } } |