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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2024-01-05 20:05:31 -0300 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 10:43:11 +1000 |
commit | b62b86a106382c64866ba8e93170a545037027ba (patch) | |
tree | 3039d69f3e08e026d4d42d52debc167323d3ff68 | |
parent | 237a2f8bcf598094f89f1c0526581d9057b392d2 (diff) | |
download | qemu-b62b86a106382c64866ba8e93170a545037027ba.zip qemu-b62b86a106382c64866ba8e93170a545037027ba.tar.gz qemu-b62b86a106382c64866ba8e93170a545037027ba.tar.bz2 |
target/riscv: make riscv_cpu_is_vendor() public
We'll use this function in target/riscv/cpu.c to implement setters that
won't allow vendor CPU options to be changed.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | target/riscv/cpu.c | 5 | ||||
-rw-r--r-- | target/riscv/cpu.h | 1 | ||||
-rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 5 |
3 files changed, 6 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8a2fd7d..1718a21 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -190,6 +190,11 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) *ext_enabled = en; } +bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; +} + const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 52648e3..bd103d2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -770,6 +770,7 @@ enum riscv_pmu_event_idx { void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +bool riscv_cpu_is_vendor(Object *cpu_obj); typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index bf8e72a..67aa2d1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -950,11 +950,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; } -static bool riscv_cpu_is_vendor(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; -} - /* * We'll get here via the following path: * |