diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2018-01-09 18:23:27 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2018-01-09 18:23:27 +0000 |
commit | 76302a95e759c7090396b0ca85cef3412e323130 (patch) | |
tree | 5d97418ad1da0018091db0abbe26860de8373864 | |
parent | 3cee4db661ab9c0fce7937b3bbfa188a1845f31f (diff) | |
parent | 5a6539e627faf9251e1db78238b9f9b870610518 (diff) | |
download | qemu-76302a95e759c7090396b0ca85cef3412e323130.zip qemu-76302a95e759c7090396b0ca85cef3412e323130.tar.gz qemu-76302a95e759c7090396b0ca85cef3412e323130.tar.bz2 |
Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into staging
target/xtensa updates:
- add libisa to the xtensa target;
- change xtensa instruction translator to use it;
- switch existing xtensa cores to use it;
- add support for a number of instructions: salt/saltu, const16,
GPIO32 group, debug mode and MMU-related;
- add disassembler for Xtensa.
# gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT
# gpg: using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20180109-xtensa:
target/xtensa: implement disassembler
target/xtensa: implement const16
target/xtensa: implement GPIO32
target/xtensa: implement salt/saltu
target/xtensa: add internal/noop SRs and opcodes
target/xtensa: drop DisasContext::litbase
target/xtensa: tests: fix memctl SR test
target/xtensa: use libisa for instruction decoding
target/xtensa: switch fsf to libisa
target/xtensa: switch dc233c to libisa
target/xtensa: switch dc232b to libisa
target/xtensa: update import_core.sh script for libisa
target/xtensa: extract FPU2000 opcode translators
target/xtensa: extract core opcode translators
target/xtensa: import libisa source
target/xtensa: pass actual frame size to the entry helper
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | MAINTAINERS | 1 | ||||
-rw-r--r-- | disas/Makefile.objs | 1 | ||||
-rw-r--r-- | disas/xtensa.c | 133 | ||||
-rw-r--r-- | include/disas/bfd.h | 1 | ||||
-rw-r--r-- | include/hw/xtensa/xtensa-isa.h | 838 | ||||
-rw-r--r-- | target/xtensa/Makefile.objs | 1 | ||||
-rw-r--r-- | target/xtensa/core-dc232b.c | 4 | ||||
-rw-r--r-- | target/xtensa/core-dc232b/xtensa-modules.c | 14105 | ||||
-rw-r--r-- | target/xtensa/core-dc233c.c | 4 | ||||
-rw-r--r-- | target/xtensa/core-dc233c/xtensa-modules.c | 15232 | ||||
-rw-r--r-- | target/xtensa/core-fsf.c | 5 | ||||
-rw-r--r-- | target/xtensa/core-fsf/xtensa-modules.c | 9841 | ||||
-rw-r--r-- | target/xtensa/cpu.c | 9 | ||||
-rw-r--r-- | target/xtensa/cpu.h | 31 | ||||
-rw-r--r-- | target/xtensa/helper.c | 37 | ||||
-rwxr-xr-x | target/xtensa/import_core.sh | 15 | ||||
-rw-r--r-- | target/xtensa/op_helper.c | 2 | ||||
-rw-r--r-- | target/xtensa/translate.c | 5860 | ||||
-rw-r--r-- | target/xtensa/xtensa-isa-internal.h | 231 | ||||
-rw-r--r-- | target/xtensa/xtensa-isa.c | 1745 | ||||
-rw-r--r-- | target/xtensa/xtensa-isa.h | 1 | ||||
-rw-r--r-- | tests/tcg/xtensa/test_sr.S | 2 |
22 files changed, 45935 insertions, 2164 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..5628322 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -259,6 +259,7 @@ S: Maintained F: target/xtensa/ F: hw/xtensa/ F: tests/tcg/xtensa/ +F: disas/xtensa.c TriCore M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> diff --git a/disas/Makefile.objs b/disas/Makefile.objs index 194648f..53556f8 100644 --- a/disas/Makefile.objs +++ b/disas/Makefile.objs @@ -21,6 +21,7 @@ common-obj-$(CONFIG_S390_DIS) += s390.o common-obj-$(CONFIG_SH4_DIS) += sh4.o common-obj-$(CONFIG_SPARC_DIS) += sparc.o common-obj-$(CONFIG_LM32_DIS) += lm32.o +common-obj-$(CONFIG_XTENSA_DIS) += xtensa.o # TODO: As long as the TCG interpreter and its generated code depend # on the QEMU target, we cannot compile the disassembler here. diff --git a/disas/xtensa.c b/disas/xtensa.c new file mode 100644 index 0000000..114326a --- /dev/null +++ b/disas/xtensa.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "disas/bfd.h" +#include "hw/xtensa/xtensa-isa.h" + +int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info) +{ + xtensa_isa isa = info->private_data; + xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc(isa); + xtensa_insnbuf slotbuf = xtensa_insnbuf_alloc(isa); + bfd_byte *buffer = g_malloc(1); + int status = info->read_memory_func(memaddr, buffer, 1, info); + xtensa_format fmt; + unsigned slot, slots; + unsigned len; + + if (status) { + info->memory_error_func(status, memaddr, info); + len = -1; + goto out; + } + len = xtensa_isa_length_from_chars(isa, buffer); + if (len == XTENSA_UNDEFINED) { + info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]); + len = 1; + goto out; + } + buffer = g_realloc(buffer, len); + status = info->read_memory_func(memaddr + 1, buffer + 1, len - 1, info); + if (status) { + info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]); + info->memory_error_func(status, memaddr + 1, info); + len = 1; + goto out; + } + + xtensa_insnbuf_from_chars(isa, insnbuf, buffer, len); + fmt = xtensa_format_decode(isa, insnbuf); + if (fmt == XTENSA_UNDEFINED) { + unsigned i; + + for (i = 0; i < len; ++i) { + info->fprintf_func(info->stream, "%s 0x%02x", + i ? ", " : ".byte ", buffer[i]); + } + goto out; + } + slots = xtensa_format_num_slots(isa, fmt); + + if (slots > 1) { + info->fprintf_func(info->stream, "{ "); + } + + for (slot = 0; slot < slots; ++slot) { + xtensa_opcode opc; + unsigned opnd, vopnd, opnds; + + if (slot) { + info->fprintf_func(info->stream, "; "); + } + xtensa_format_get_slot(isa, fmt, slot, insnbuf, slotbuf); + opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf); + if (opc == XTENSA_UNDEFINED) { + info->fprintf_func(info->stream, "???"); + continue; + } + opnds = xtensa_opcode_num_operands(isa, opc); + + info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc)); + + for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + if (xtensa_operand_is_visible(isa, opc, opnd)) { + uint32_t v = 0xbadc0de; + int rc; + + info->fprintf_func(info->stream, vopnd ? ", " : "\t"); + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + slotbuf, &v); + rc = xtensa_operand_decode(isa, opc, opnd, &v); + if (rc == XTENSA_UNDEFINED) { + info->fprintf_func(info->stream, "???"); + } else if (xtensa_operand_is_register(isa, opc, opnd)) { + xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); + + info->fprintf_func(info->stream, "%s%d", + xtensa_regfile_shortname(isa, rf), v); + } else if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { + xtensa_operand_undo_reloc(isa, opc, opnd, &v, memaddr); + info->fprintf_func(info->stream, "0x%x", v); + } else { + info->fprintf_func(info->stream, "%d", v); + } + ++vopnd; + } + } + } + if (slots > 1) { + info->fprintf_func(info->stream, " }"); + } + +out: + g_free(buffer); + xtensa_insnbuf_free(isa, insnbuf); + xtensa_insnbuf_free(isa, slotbuf); + + return len; +} diff --git a/include/disas/bfd.h b/include/disas/bfd.h index 46c7ec3..9324537 100644 --- a/include/disas/bfd.h +++ b/include/disas/bfd.h @@ -428,6 +428,7 @@ int print_insn_ia64 (bfd_vma, disassemble_info*); int print_insn_lm32 (bfd_vma, disassemble_info*); int print_insn_big_nios2 (bfd_vma, disassemble_info*); int print_insn_little_nios2 (bfd_vma, disassemble_info*); +int print_insn_xtensa (bfd_vma, disassemble_info*); #if 0 /* Fetch the disassembler for a given BFD, if that support is available. */ diff --git a/include/hw/xtensa/xtensa-isa.h b/include/hw/xtensa/xtensa-isa.h new file mode 100644 index 0000000..353f82b --- /dev/null +++ b/include/hw/xtensa/xtensa-isa.h @@ -0,0 +1,838 @@ +/* Interface definition for configurable Xtensa ISA support. + * + * Copyright (c) 2001-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Version number: This is intended to help support code that works with + * versions of this library from multiple Xtensa releases. + */ + +#define XTENSA_ISA_VERSION 7000 + +/* + * This file defines the interface to the Xtensa ISA library. This + * library contains most of the ISA-specific information for a + * particular Xtensa processor. For example, the set of valid + * instructions, their opcode encodings and operand fields are all + * included here. + * + * This interface basically defines a number of abstract data types. + * + * . an instruction buffer - for holding the raw instruction bits + * . ISA info - information about the ISA as a whole + * . instruction formats - instruction size and slot structure + * . opcodes - information about individual instructions + * . operands - information about register and immediate instruction operands + * . stateOperands - information about processor state instruction operands + * . interfaceOperands - information about interface instruction operands + * . register files - register file information + * . processor states - internal processor state information + * . system registers - "special registers" and "user registers" + * . interfaces - TIE interfaces that are external to the processor + * . functional units - TIE shared functions + * + * The interface defines a set of functions to access each data type. + * With the exception of the instruction buffer, the internal + * representations of the data structures are hidden. All accesses must + * be made through the functions defined here. + */ + +typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa; + + +/* + * Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are + * represented here using sequential integers beginning with 0. The + * specific values are only fixed for a particular instantiation of an + * xtensa_isa structure, so these values should only be used + * internally. + */ + +typedef int xtensa_opcode; +typedef int xtensa_format; +typedef int xtensa_regfile; +typedef int xtensa_state; +typedef int xtensa_sysreg; +typedef int xtensa_interface; +typedef int xtensa_funcUnit; + + +/* Define a unique value for undefined items. */ + +#define XTENSA_UNDEFINED -1 + + +/* + * Overview of using this interface to decode/encode instructions: + * + * Each Xtensa instruction is associated with a particular instruction + * format, where the format defines a fixed number of slots for + * operations. The formats for the core Xtensa ISA have only one slot, + * but FLIX instructions may have multiple slots. Within each slot, + * there is a single opcode and some number of associated operands. + * + * The encoding and decoding functions operate on instruction buffers, + * not on the raw bytes of the instructions. The same instruction + * buffer data structure is used for both entire instructions and + * individual slots in those instructions -- the contents of a slot need + * to be extracted from or inserted into the buffer for the instruction + * as a whole. + * + * Decoding an instruction involves first finding the format, which + * identifies the number of slots, and then decoding each slot + * separately. A slot is decoded by finding the opcode and then using + * the opcode to determine how many operands there are. For example: + * + * xtensa_insnbuf_from_chars + * xtensa_format_decode + * for each slot { + * xtensa_format_get_slot + * xtensa_opcode_decode + * for each operand { + * xtensa_operand_get_field + * xtensa_operand_decode + * } + * } + * + * Encoding an instruction is roughly the same procedure in reverse: + * + * xtensa_format_encode + * for each slot { + * xtensa_opcode_encode + * for each operand { + * xtensa_operand_encode + * xtensa_operand_set_field + * } + * xtensa_format_set_slot + * } + * xtensa_insnbuf_to_chars + */ + + +/* Error handling. */ + +/* + * Error codes. The code for the most recent error condition can be + * retrieved with the "errno" function. For any result other than + * xtensa_isa_ok, an error message containing additional information + * about the problem can be retrieved using the "error_msg" function. + * The error messages are stored in an internal buffer, which should + * not be freed and may be overwritten by subsequent operations. + */ + +typedef enum xtensa_isa_status_enum { + xtensa_isa_ok = 0, + xtensa_isa_bad_format, + xtensa_isa_bad_slot, + xtensa_isa_bad_opcode, + xtensa_isa_bad_operand, + xtensa_isa_bad_field, + xtensa_isa_bad_iclass, + xtensa_isa_bad_regfile, + xtensa_isa_bad_sysreg, + xtensa_isa_bad_state, + xtensa_isa_bad_interface, + xtensa_isa_bad_funcUnit, + xtensa_isa_wrong_slot, + xtensa_isa_no_field, + xtensa_isa_out_of_memory, + xtensa_isa_buffer_overflow, + xtensa_isa_internal_error, + xtensa_isa_bad_value +} xtensa_isa_status; + +xtensa_isa_status xtensa_isa_errno(xtensa_isa isa); + +char *xtensa_isa_error_msg(xtensa_isa isa); + + + +/* Instruction buffers. */ + +typedef uint32_t xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + + +/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */ + +int xtensa_insnbuf_size(xtensa_isa isa); + + +/* Allocate an xtensa_insnbuf of the right size. */ + +xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa); + + +/* Release an xtensa_insnbuf. */ + +void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf); + + +/* + * Conversion between raw memory (char arrays) and our internal + * instruction representation. This is complicated by the Xtensa ISA's + * variable instruction lengths. When converting to chars, the buffer + * must contain a valid instruction so we know how many bytes to copy; + * thus, the "to_chars" function returns the number of bytes copied or + * XTENSA_UNDEFINED on error. The "from_chars" function first reads the + * minimal number of bytes required to decode the instruction length and + * then proceeds to copy the entire instruction into the buffer; if the + * memory does not contain a valid instruction, it copies the maximum + * number of bytes required for the longest Xtensa instruction. The + * "num_chars" argument may be used to limit the number of bytes that + * can be read or written. Otherwise, if "num_chars" is zero, the + * functions may read or write past the end of the code. + */ + +int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn, + unsigned char *cp, int num_chars); + +void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn, + const unsigned char *cp, int num_chars); + + + +/* ISA information. */ + +/* Initialize the ISA information. */ + +xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p, + char **error_msg_p); + + +/* Deallocate an xtensa_isa structure. */ + +void xtensa_isa_free(xtensa_isa isa); + + +/* Get the maximum instruction size in bytes. */ + +int xtensa_isa_maxlength(xtensa_isa isa); + + +/* + * Decode the length in bytes of an instruction in raw memory (not an + * insnbuf). This function reads only the minimal number of bytes + * required to decode the instruction length. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp); + + +/* + * Get the number of stages in the processor's pipeline. The pipeline + * stage values returned by other functions in this library will range + * from 0 to N-1, where N is the value returned by this function. + * Note that the stage numbers used here may not correspond to the + * actual processor hardware, e.g., the hardware may have additional + * stages before stage 0. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_num_pipe_stages(xtensa_isa isa); + + +/* Get the number of various entities that are defined for this processor. */ + +int xtensa_isa_num_formats(xtensa_isa isa); + +int xtensa_isa_num_opcodes(xtensa_isa isa); + +int xtensa_isa_num_regfiles(xtensa_isa isa); + +int xtensa_isa_num_states(xtensa_isa isa); + +int xtensa_isa_num_sysregs(xtensa_isa isa); + +int xtensa_isa_num_interfaces(xtensa_isa isa); + +int xtensa_isa_num_funcUnits(xtensa_isa isa); + + + +/* Instruction formats. */ + +/* Get the name of a format. Returns null on error. */ + +const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt); + + +/* + * Given a format name, return the format number. Returns + * XTENSA_UNDEFINED if the name is not a valid format. + */ + +xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname); + + +/* + * Decode the instruction format from a binary instruction buffer. + * Returns XTENSA_UNDEFINED if the format is not recognized. + */ + +xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn); + + +/* + * Set the instruction format field(s) in a binary instruction buffer. + * All the other fields are set to zero. Returns non-zero on error. + */ + +int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt, + xtensa_insnbuf insn); + + +/* + * Find the length (in bytes) of an instruction. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_format_length(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the number of slots in an instruction. Returns XTENSA_UNDEFINED + * on error. + */ + +int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the opcode for a no-op in a particular slot. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt, + int slot); + + +/* + * Get the bits for a specified slot out of an insnbuf for the + * instruction as a whole and put them into an insnbuf for that one + * slot, and do the opposite to set a slot. Return non-zero on error. + */ + +int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf); + +int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf); + + + +/* Opcode information. */ + +/* + * Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + * the name is not a valid opcode mnemonic. + */ + +xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname); + + +/* + * Decode the opcode for one instruction slot from a binary instruction + * buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is + * illegal. + */ + +xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf); + + +/* + * Set the opcode field(s) for an instruction slot. All other fields + * in the slot are set to zero. Returns non-zero if the opcode cannot + * be encoded. + */ + +int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc); + + +/* Get the mnemonic name for an opcode. Returns null on error. */ + +const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc); + + +/* Check various properties of opcodes. These functions return 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. The instructions are classified as + * follows: + * + * branch: conditional branch; may fall through to next instruction (B*) + * jump: unconditional branch (J, JX, RET*, RF*) + * loop: zero-overhead loop (LOOP*) + * call: unconditional call; control returns to next instruction (CALL*) + * + * For the opcodes that affect control flow in some way, the branch + * target may be specified by an immediate operand or it may be an + * address stored in a register. You can distinguish these by + * checking if the instruction has a PC-relative immediate + * operand. + */ + +int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Find the number of ordinary operands, state operands, and interface + * operands for an instruction. These return XTENSA_UNDEFINED on + * error. + */ + +int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Get functional unit usage requirements for an opcode. Each "use" + * is identified by a <functional unit, pipeline stage> pair. The + * "num_funcUnit_uses" function returns the number of these "uses" or + * XTENSA_UNDEFINED on error. The "funcUnit_use" function returns + * a pointer to a "use" pair or null on error. + */ + +typedef struct xtensa_funcUnit_use_struct { + xtensa_funcUnit unit; + int stage; +} xtensa_funcUnit_use; + +int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc); + +xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa, + xtensa_opcode opc, int u); + + + +/* Operand information. */ + +/* Get the name of an operand. Returns null on error. */ + +const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some operands are "invisible", i.e., not explicitly specified in + * assembly language. When assembling an instruction, you need not set + * the values of invisible operands, since they are either hardwired or + * derived from other field values. The values of invisible operands + * can be examined in the same way as other operands, but remember that + * an invisible operand may get its value from another visible one, so + * the entire instruction must be available before examining the + * invisible operand values. This function returns 1 if an operand is + * visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note + * that whether an operand is visible is orthogonal to whether it is + * "implicit", i.e., whether it is encoded in a field in the + * instruction. + */ + +int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an operand is an input ('i'), output ('o'), or inout ('m') + * operand. Note: The output operand of a conditional assignment + * (e.g., movnez) appears here as an inout ('m') even if it is declared + * in the TIE code as an output ('o'); this allows the compiler to + * properly handle register allocation for conditional assignments. + * Returns 0 on error. + */ + +char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Get and set the raw (encoded) value of the field for the specified + * operand. The "set" function does not check if the value fits in the + * field; that is done by the "encode" function below. Both of these + * functions return non-zero on error, e.g., if the field is not defined + * for the specified slot. + */ + +int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32_t *valp); + +int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32_t val); + + +/* + * Encode and decode operands. The raw bits in the operand field may + * be encoded in a variety of different ways. These functions hide + * the details of that encoding. The result values are returned through + * the argument pointer. The return value is non-zero on error. + */ + +int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + +int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + + +/* + * An operand may be either a register operand or an immediate of some + * sort (e.g., PC-relative or not). The "is_register" function returns + * 0 if the operand is an immediate, 1 if it is a register, and + * XTENSA_UNDEFINED on error. The "regfile" function returns the + * regfile for a register operand, or XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd); + +xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc, + int opnd); + + +/* + * Register operands may span multiple consecutive registers, e.g., a + * 64-bit data type may occupy two 32-bit registers. Only the first + * register is encoded in the operand field. This function specifies + * the number of consecutive registers occupied by this operand. For + * non-register operands, the return value is undefined. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some register operands do not completely identify the register being + * accessed. For example, the operand value may be added to an internal + * state value. By definition, this implies that the corresponding + * regfile is not allocatable. Unknown registers should generally be + * treated with worst-case assumptions. The function returns 0 if the + * register value is unknown, 1 if known, and XTENSA_UNDEFINED on + * error. + */ + +int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an immediate operand is PC-relative. Returns 0 for register + * operands and non-PC-relative immediates, 1 for PC-relative + * immediates, and XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * For PC-relative offset operands, the interpretation of the offset may + * vary between opcodes, e.g., is it relative to the current PC or that + * of the next instruction? The following functions are defined to + * perform PC-relative relocations and to undo them (as in the + * disassembler). The "do_reloc" function takes the desired address + * value and the PC of the current instruction and sets the value to the + * corresponding PC-relative offset (which can then be encoded and + * stored into the operand field). The "undo_reloc" function takes the + * unencoded offset value and the current PC and sets the value to the + * appropriate address. The return values are non-zero on error. Note + * that these functions do not replace the encode/decode functions; the + * operands must be encoded/decoded separately and the encode functions + * are responsible for detecting invalid operand values. + */ + +int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + +int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + + + +/* State Operands. */ + +/* + * Get the state accessed by a state operand. Returns XTENSA_UNDEFINED + * on error. + */ + +xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc, + int stOp); + + +/* + * Check if a state operand is an input ('i'), output ('o'), or inout + * ('m') operand. Returns 0 on error. + */ + +char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp); + + + +/* Interface Operands. */ + +/* + * Get the external interface accessed by an interface operand. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa, + xtensa_opcode opc, + int ifOp); + + + +/* Register Files. */ + +/* + * Regfiles include both "real" regfiles and "views", where a view + * allows a group of adjacent registers in a real "parent" regfile to be + * viewed as a single register. A regfile view has all the same + * properties as its parent except for its (long) name, bit width, number + * of entries, and default ctype. You can use the parent function to + * distinguish these two classes. + */ + +/* + * Look up a regfile by either its name or its abbreviated "short name". + * Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function + * ignores "view" regfiles since they always have the same shortname as + * their parents. + */ + +xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name); + +xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa, + const char *shortname); + + +/* + * Get the name or abbreviated "short name" of a regfile. + * Returns null on error. + */ + +const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf); + +const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the parent regfile of a "view" regfile. If the regfile is not a + * view, the result is the same as the input parameter. Returns + * XTENSA_UNDEFINED on error. + */ + +xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the bit width of a regfile or regfile view. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the number of regfile entries. Returns XTENSA_UNDEFINED on + * error. + */ + +int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf); + + + +/* Processor States. */ + +/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */ + +xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name); + + +/* Get the name for a processor state. Returns null on error. */ + +const char *xtensa_state_name(xtensa_isa isa, xtensa_state st); + + +/* + * Get the bit width for a processor state. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st); + + +/* + * Check if a state is exported from the processor core. Returns 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st); + + +/* + * Check for a "shared_or" state. Returns 0 if the condition is false, + * 1 if the condition is true, and XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st); + + + +/* Sysregs ("special registers" and "user registers"). */ + +/* + * Look up a register by its number and whether it is a "user register" + * or a "special register". Returns XTENSA_UNDEFINED if the sysreg does + * not exist. + */ + +xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user); + + +/* + * Check if there exists a sysreg with a given name. + * If not, this function returns XTENSA_UNDEFINED. + */ + +xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name); + + +/* Get the name of a sysreg. Returns null on error. */ + +const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* Get the register number. Returns XTENSA_UNDEFINED on error. */ + +int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* + * Check if a sysreg is a "special register" or a "user register". + * Returns 0 for special registers, 1 for user registers and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg); + + + +/* Interfaces. */ + +/* + * Find an interface by name. The return value is XTENSA_UNDEFINED if + * the specified interface is not found. + */ + +xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname); + + +/* Get the name of an interface. Returns null on error. */ + +const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf); + + +/* + * Get the bit width for an interface. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if an interface is an input ('i') or output ('o') with respect + * to the Xtensa processor core. Returns 0 on error. + */ + +char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if accessing an interface has potential side effects. + * Currently "data" interfaces have side effects and "control" + * interfaces do not. Returns 1 if there are side effects, 0 if not, + * and XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf); + + +/* + * Some interfaces may be related such that accessing one interface + * has side effects on a set of related interfaces. The interfaces + * are partitioned into equivalence classes of related interfaces, and + * each class is assigned a unique identifier number. This function + * returns the class identifier for an interface, or XTENSA_UNDEFINED + * on error. These identifiers can be compared to determine if two + * interfaces are related; the specific values of the identifiers have + * no particular meaning otherwise. + */ + +int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf); + + +/* Functional Units. */ + +/* + * Find a functional unit by name. The return value is XTENSA_UNDEFINED if + * the specified unit is not found. + */ + +xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname); + + +/* Get the name of a functional unit. Returns null on error. */ + +const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun); + + +/* + * Functional units may be replicated. See how many instances of a + * particular function unit exist. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun); + + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index 481de91..0429706 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -3,5 +3,6 @@ obj-y += core-dc232b.o obj-y += core-dc233c.o obj-y += core-fsf.o obj-$(CONFIG_SOFTMMU) += monitor.o +obj-y += xtensa-isa.o obj-y += translate.o op_helper.o helper.o cpu.o obj-y += gdbstub.o diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c index bb8ed41..fe80582 100644 --- a/target/xtensa/core-dc232b.c +++ b/target/xtensa/core-dc232b.c @@ -34,6 +34,9 @@ #include "core-dc232b/core-isa.h" #include "overlay_tool.h" +#define xtensa_modules xtensa_modules_dc232b +#include "core-dc232b/xtensa-modules.c" + static XtensaConfig dc232b __attribute__((unused)) = { .name = "dc232b", .gdb_regmap = { @@ -43,6 +46,7 @@ static XtensaConfig dc232b __attribute__((unused)) = { #include "core-dc232b/gdb-config.c" } }, + .isa_internal = &xtensa_modules, .clock_freq_khz = 10000, DEFAULT_SECTIONS }; diff --git a/target/xtensa/core-dc232b/xtensa-modules.c b/target/xtensa/core-dc232b/xtensa-modules.c new file mode 100644 index 0000000..2e103cd --- /dev/null +++ b/target/xtensa/core-dc232b/xtensa-modules.c @@ -0,0 +1,14105 @@ +/* Xtensa configuration-specific ISA information. + Copyright 2003, 2004, 2005 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include <xtensa-isa.h> +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "THREADPTR", 231, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 70 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 73 + +/* Macros for xtensa_state numbers (for use in iclasses because the + state numbers are not available when the iclass table is generated). */ + +#define STATE_LCOUNT 0 +#define STATE_PC 1 +#define STATE_ICOUNT 2 +#define STATE_DDR 3 +#define STATE_INTERRUPT 4 +#define STATE_CCOUNT 5 +#define STATE_XTSYNC 6 +#define STATE_VECBASE 7 +#define STATE_EPC1 8 +#define STATE_EPC2 9 +#define STATE_EPC3 10 +#define STATE_EPC4 11 +#define STATE_EPC5 12 +#define STATE_EPC6 13 +#define STATE_EPC7 14 +#define STATE_EXCSAVE1 15 +#define STATE_EXCSAVE2 16 +#define STATE_EXCSAVE3 17 +#define STATE_EXCSAVE4 18 +#define STATE_EXCSAVE5 19 +#define STATE_EXCSAVE6 20 +#define STATE_EXCSAVE7 21 +#define STATE_EPS2 22 +#define STATE_EPS3 23 +#define STATE_EPS4 24 +#define STATE_EPS5 25 +#define STATE_EPS6 26 +#define STATE_EPS7 27 +#define STATE_EXCCAUSE 28 +#define STATE_PSINTLEVEL 29 +#define STATE_PSUM 30 +#define STATE_PSWOE 31 +#define STATE_PSRING 32 +#define STATE_PSEXCM 33 +#define STATE_DEPC 34 +#define STATE_EXCVADDR 35 +#define STATE_WindowBase 36 +#define STATE_WindowStart 37 +#define STATE_PSCALLINC 38 +#define STATE_PSOWB 39 +#define STATE_LBEG 40 +#define STATE_LEND 41 +#define STATE_SAR 42 +#define STATE_THREADPTR 43 +#define STATE_LITBADDR 44 +#define STATE_LITBEN 45 +#define STATE_MISC0 46 +#define STATE_MISC1 47 +#define STATE_ACC 48 +#define STATE_InOCDMode 49 +#define STATE_INTENABLE 50 +#define STATE_DBREAKA0 51 +#define STATE_DBREAKC0 52 +#define STATE_DBREAKA1 53 +#define STATE_DBREAKC1 54 +#define STATE_IBREAKA0 55 +#define STATE_IBREAKA1 56 +#define STATE_IBREAKENABLE 57 +#define STATE_ICOUNTLEVEL 58 +#define STATE_DEBUGCAUSE 59 +#define STATE_DBNUM 60 +#define STATE_CCOMPARE0 61 +#define STATE_CCOMPARE1 62 +#define STATE_CCOMPARE2 63 +#define STATE_ASID3 64 +#define STATE_ASID2 65 +#define STATE_ASID1 66 +#define STATE_INSTPGSZID4 67 +#define STATE_DATAPGSZID4 68 +#define STATE_PTBASE 69 +#define STATE_CPENABLE 70 +#define STATE_SCOMPARE1 71 +#define STATE_EXPSTATE 72 + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", 0, 32, 32 }, + { "MR", "m", 1, 32, 4 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mx_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_my_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +Operand_my_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mw_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr1_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr2_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr3_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static int +Operand_tp7_decode (uint32 *valp) +{ + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; +} + +static int +Operand_tp7_encode (uint32 *valp) +{ + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; +} + +static int +Operand_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; +} + +static int +Operand_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", 3, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", 26, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", 14, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", 0, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", 48, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", 49, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", 50, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", 51, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", 14, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", 14, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", 34, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", 33, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", 0, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", 14, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", 14, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", 4, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", 4, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", 4, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", 13, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", 4, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", 4, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", 6, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", 18, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", 13, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", 3, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", 7, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "mx", 43, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_mx_encode, Operand_mx_decode, + 0, 0 }, + { "my", 42, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_my_encode, Operand_my_decode, + 0, 0 }, + { "mw", 41, 1, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_mw_encode, Operand_mw_decode, + 0, 0 }, + { "mr0", 52, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr0_encode, Operand_mr0_decode, + 0, 0 }, + { "mr1", 53, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr1_encode, Operand_mr1_decode, + 0, 0 }, + { "mr2", 54, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr2_encode, Operand_mr2_decode, + 0, 0 }, + { "mr3", 55, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr3_encode, Operand_mr3_decode, + 0, 0 }, + { "immt", 0, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", 5, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "tp7", 0, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", 44, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", 45, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, + { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, + { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, + { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, + { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, + { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, + { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, + { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, + { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, + { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, + { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 }, + { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 } +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { 11 /* ars_entry */ }, 's' }, + { { 4 /* ars */ }, 'i' }, + { { 1 /* uimm12x8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { 2 /* simm4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 16 /* ai4const */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 15 /* uimm6 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { 4 /* ars */ }, 'o' }, + { { 14 /* simm7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { 3 /* arr */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 23 /* simm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 24 /* simm8x256 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 17 /* b4const */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 47 /* bbi */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 18 /* b4constu */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 30 /* label12 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 62 /* sae */ }, 'i' }, + { { 27 /* op2p1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { 31 /* soffset */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { 6 /* art */ }, 'o' }, + { { 32 /* uimm16x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 25 /* simm12b */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { 3 /* arr */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { 66 /* sas */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 26 /* msalp32 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 64 /* sargt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { 6 /* art */ }, 'o' }, + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' }, + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' }, + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { 6 /* art */ }, 'o' }, + { { 36 /* mr0 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { 6 /* art */ }, 'i' }, + { { 36 /* mr0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { 6 /* art */ }, 'm' }, + { { 36 /* mr0 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { 6 /* art */ }, 'o' }, + { { 37 /* mr1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { 6 /* art */ }, 'i' }, + { { 37 /* mr1 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { 6 /* art */ }, 'm' }, + { { 37 /* mr1 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { 6 /* art */ }, 'o' }, + { { 38 /* mr2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { 6 /* art */ }, 'i' }, + { { 38 /* mr2 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { 6 /* art */ }, 'm' }, + { { 38 /* mr2 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { 6 /* art */ }, 'o' }, + { { 39 /* mr3 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { 6 /* art */ }, 'i' }, + { { 39 /* mr3 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { 6 /* art */ }, 'm' }, + { { 39 /* mr3 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { 41 /* imms */ }, 'i' }, + { { 40 /* immt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { 41 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { 41 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 42 /* tp7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 42 /* tp7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { 6 /* art */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { 3 /* arr */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + 0 /* IMPWIRE */ +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { 91 /* bitindex */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { 91 /* bitindex */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_mul16_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", 0 /* xt_iclass_excw */, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", 1 /* xt_iclass_rfe */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", 2 /* xt_iclass_rfde */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", 3 /* xt_iclass_syscall */, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", 4 /* xt_iclass_simcall */, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", 5 /* xt_iclass_call12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", 6 /* xt_iclass_call8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", 7 /* xt_iclass_call4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", 8 /* xt_iclass_callx12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", 9 /* xt_iclass_callx8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", 10 /* xt_iclass_callx4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", 11 /* xt_iclass_entry */, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", 12 /* xt_iclass_movsp */, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", 13 /* xt_iclass_rotw */, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", 16 /* xt_iclass_l32e */, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", 17 /* xt_iclass_s32e */, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", 24 /* xt_iclass_add.n */, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", 25 /* xt_iclass_addi.n */, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", 27 /* xt_iclass_ill.n */, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", 28 /* xt_iclass_loadi4 */, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", 29 /* xt_iclass_mov.n */, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", 30 /* xt_iclass_movi.n */, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", 31 /* xt_iclass_nopn */, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", 32 /* xt_iclass_retn */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", 33 /* xt_iclass_storei4 */, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", 34 /* rur_threadptr */, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", 35 /* wur_threadptr */, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", 36 /* xt_iclass_addi */, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", 37 /* xt_iclass_addmi */, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", 38 /* xt_iclass_addsub */, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", 38 /* xt_iclass_addsub */, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", 39 /* xt_iclass_bit */, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", 39 /* xt_iclass_bit */, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", 39 /* xt_iclass_bit */, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", 45 /* xt_iclass_call0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", 46 /* xt_iclass_callx0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", 47 /* xt_iclass_exti */, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", 48 /* xt_iclass_ill */, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", 49 /* xt_iclass_jump */, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", 50 /* xt_iclass_jumpx */, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", 51 /* xt_iclass_l16ui */, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", 52 /* xt_iclass_l16si */, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", 53 /* xt_iclass_l32i */, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", 54 /* xt_iclass_l32r */, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", 55 /* xt_iclass_l8i */, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", 56 /* xt_iclass_loop */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", 58 /* xt_iclass_movi */, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", 59 /* xt_iclass_movz */, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", 59 /* xt_iclass_movz */, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", 59 /* xt_iclass_movz */, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", 59 /* xt_iclass_movz */, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", 60 /* xt_iclass_neg */, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", 60 /* xt_iclass_neg */, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", 61 /* xt_iclass_nop */, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", 62 /* xt_iclass_return */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", 63 /* xt_iclass_s16i */, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", 64 /* xt_iclass_s32i */, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", 65 /* xt_iclass_s8i */, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", 66 /* xt_iclass_sar */, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", 66 /* xt_iclass_sar */, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", 67 /* xt_iclass_sari */, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", 68 /* xt_iclass_shifts */, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", 69 /* xt_iclass_shiftst */, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", 70 /* xt_iclass_shiftt */, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", 70 /* xt_iclass_shiftt */, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", 71 /* xt_iclass_slli */, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", 72 /* xt_iclass_srai */, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", 73 /* xt_iclass_srli */, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", 74 /* xt_iclass_memw */, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", 75 /* xt_iclass_extw */, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", 76 /* xt_iclass_isync */, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", 77 /* xt_iclass_sync */, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", 77 /* xt_iclass_sync */, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", 77 /* xt_iclass_sync */, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", 78 /* xt_iclass_rsil */, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", 79 /* xt_iclass_rsr.lend */, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", 80 /* xt_iclass_wsr.lend */, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", 81 /* xt_iclass_xsr.lend */, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", 88 /* xt_iclass_rsr.sar */, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", 89 /* xt_iclass_wsr.sar */, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", 90 /* xt_iclass_xsr.sar */, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", 94 /* xt_iclass_rsr.176 */, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "rsr.208", 95 /* xt_iclass_rsr.208 */, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", 96 /* xt_iclass_rsr.ps */, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", 97 /* xt_iclass_wsr.ps */, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", 98 /* xt_iclass_xsr.ps */, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", 162 /* xt_iclass_rsr.depc */, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", 163 /* xt_iclass_wsr.depc */, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", 164 /* xt_iclass_xsr.depc */, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", 174 /* xt_iclass_rsr.prid */, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", 188 /* xt_iclass_mac16_l */, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", 188 /* xt_iclass_mac16_l */, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "mul16u", 189 /* xt_iclass_mul16 */, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", 189 /* xt_iclass_mul16 */, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "rsr.m0", 190 /* xt_iclass_rsr.m0 */, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", 191 /* xt_iclass_wsr.m0 */, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", 192 /* xt_iclass_xsr.m0 */, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", 193 /* xt_iclass_rsr.m1 */, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", 194 /* xt_iclass_wsr.m1 */, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", 195 /* xt_iclass_xsr.m1 */, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", 196 /* xt_iclass_rsr.m2 */, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", 197 /* xt_iclass_wsr.m2 */, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", 198 /* xt_iclass_xsr.m2 */, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", 199 /* xt_iclass_rsr.m3 */, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", 200 /* xt_iclass_wsr.m3 */, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", 201 /* xt_iclass_xsr.m3 */, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", 208 /* xt_iclass_rfi */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", 209 /* xt_iclass_wait */, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", 211 /* xt_iclass_wsr.intset */, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", 216 /* xt_iclass_break */, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", 217 /* xt_iclass_break.n */, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", 242 /* xt_iclass_rsr.icount */, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", 243 /* xt_iclass_wsr.icount */, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", 244 /* xt_iclass_xsr.icount */, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", 251 /* xt_iclass_rfdo */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", 252 /* xt_iclass_rfdd */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", 266 /* xt_iclass_icache */, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", 266 /* xt_iclass_icache */, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", 268 /* xt_iclass_icache_inv */, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", 269 /* xt_iclass_licx */, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", 269 /* xt_iclass_licx */, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", 270 /* xt_iclass_sicx */, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", 270 /* xt_iclass_sicx */, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", 271 /* xt_iclass_dcache */, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", 271 /* xt_iclass_dcache */, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", 272 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", 272 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", 273 /* xt_iclass_dcache_inv */, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", 273 /* xt_iclass_dcache_inv */, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", 276 /* xt_iclass_sdct */, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", 277 /* xt_iclass_ldct */, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", 290 /* xt_iclass_idtlb */, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", 292 /* xt_iclass_wdtlb */, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", 293 /* xt_iclass_iitlb */, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", 294 /* xt_iclass_ritlb */, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", 294 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", 294 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", 295 /* xt_iclass_witlb */, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", 296 /* xt_iclass_ldpte */, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", 297 /* xt_iclass_hwwitlba */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", 302 /* xt_iclass_clamp */, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", 303 /* xt_iclass_minmax */, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", 303 /* xt_iclass_minmax */, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", 303 /* xt_iclass_minmax */, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", 303 /* xt_iclass_minmax */, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", 304 /* xt_iclass_nsa */, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", 304 /* xt_iclass_nsa */, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", 305 /* xt_iclass_sx */, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", 306 /* xt_iclass_l32ai */, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", 307 /* xt_iclass_s32ri */, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", 308 /* xt_iclass_s32c1i */, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "quou", 312 /* xt_iclass_div */, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", 312 /* xt_iclass_div */, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", 312 /* xt_iclass_div */, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", 312 /* xt_iclass_div */, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "mull", 313 /* xt_mul32 */, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rur.expstate", 314 /* rur_expstate */, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", 315 /* wur_expstate */, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", 316 /* iclass_READ_IMPWIRE */, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 79; /* ill */ + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 98; /* ret */ + case 1: + return 14; /* retw */ + case 2: + return 81; /* jx */ + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 77; /* callx0 */ + case 1: + return 10; /* callx4 */ + case 2: + return 9; /* callx8 */ + case 3: + return 8; /* callx12 */ + } + break; + } + break; + case 1: + return 12; /* movsp */ + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 116; /* isync */ + case 1: + return 117; /* rsync */ + case 2: + return 118; /* esync */ + case 3: + return 119; /* dsync */ + case 8: + return 0; /* excw */ + case 12: + return 114; /* memw */ + case 13: + return 115; /* extw */ + case 15: + return 97; /* nop */ + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 1; /* rfe */ + case 2: + return 2; /* rfde */ + case 4: + return 16; /* rfwo */ + case 5: + return 17; /* rfwu */ + } + break; + case 1: + return 310; /* rfi */ + } + break; + case 4: + return 318; /* break */ + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 3; /* syscall */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 4; /* simcall */ + break; + } + break; + case 6: + return 120; /* rsil */ + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return 311; /* waiti */ + break; + } + break; + case 1: + return 49; /* and */ + case 2: + return 50; /* or */ + case 3: + return 51; /* xor */ + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 102; /* ssr */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 103; /* ssl */ + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return 104; /* ssa8l */ + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return 105; /* ssa8b */ + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return 106; /* ssai */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return 13; /* rotw */ + break; + case 14: + return 426; /* nsa */ + case 15: + return 427; /* nsau */ + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return 416; /* hwwitlba */ + case 3: + return 412; /* ritlb0 */ + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return 410; /* iitlb */ + break; + case 5: + return 411; /* pitlb */ + case 6: + return 414; /* witlb */ + case 7: + return 413; /* ritlb1 */ + case 9: + return 417; /* hwwdtlba */ + case 11: + return 407; /* rdtlb0 */ + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return 405; /* idtlb */ + break; + case 13: + return 406; /* pdtlb */ + case 14: + return 409; /* wdtlb */ + case 15: + return 408; /* rdtlb1 */ + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 95; /* neg */ + case 1: + return 96; /* abs */ + } + break; + case 8: + return 41; /* add */ + case 9: + return 43; /* addx2 */ + case 10: + return 44; /* addx4 */ + case 11: + return 45; /* addx8 */ + case 12: + return 42; /* sub */ + case 13: + return 46; /* subx2 */ + case 14: + return 47; /* subx4 */ + case 15: + return 48; /* subx8 */ + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return 111; /* slli */ + case 2: + case 3: + return 112; /* srai */ + case 4: + return 113; /* srli */ + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 129; /* xsr.lbeg */ + case 1: + return 123; /* xsr.lend */ + case 2: + return 126; /* xsr.lcount */ + case 3: + return 132; /* xsr.sar */ + case 5: + return 135; /* xsr.litbase */ + case 12: + return 434; /* xsr.scompare1 */ + case 16: + return 306; /* xsr.acclo */ + case 17: + return 309; /* xsr.acchi */ + case 32: + return 294; /* xsr.m0 */ + case 33: + return 297; /* xsr.m1 */ + case 34: + return 300; /* xsr.m2 */ + case 35: + return 303; /* xsr.m3 */ + case 72: + return 22; /* xsr.windowbase */ + case 73: + return 25; /* xsr.windowstart */ + case 83: + return 395; /* xsr.ptevaddr */ + case 90: + return 398; /* xsr.rasid */ + case 91: + return 401; /* xsr.itlbcfg */ + case 92: + return 404; /* xsr.dtlbcfg */ + case 96: + return 340; /* xsr.ibreakenable */ + case 104: + return 352; /* xsr.ddr */ + case 128: + return 334; /* xsr.ibreaka0 */ + case 129: + return 337; /* xsr.ibreaka1 */ + case 144: + return 322; /* xsr.dbreaka0 */ + case 145: + return 328; /* xsr.dbreaka1 */ + case 160: + return 325; /* xsr.dbreakc0 */ + case 161: + return 331; /* xsr.dbreakc1 */ + case 177: + return 143; /* xsr.epc1 */ + case 178: + return 149; /* xsr.epc2 */ + case 179: + return 155; /* xsr.epc3 */ + case 180: + return 161; /* xsr.epc4 */ + case 181: + return 167; /* xsr.epc5 */ + case 182: + return 173; /* xsr.epc6 */ + case 183: + return 179; /* xsr.epc7 */ + case 192: + return 206; /* xsr.depc */ + case 194: + return 185; /* xsr.eps2 */ + case 195: + return 188; /* xsr.eps3 */ + case 196: + return 191; /* xsr.eps4 */ + case 197: + return 194; /* xsr.eps5 */ + case 198: + return 197; /* xsr.eps6 */ + case 199: + return 200; /* xsr.eps7 */ + case 209: + return 146; /* xsr.excsave1 */ + case 210: + return 152; /* xsr.excsave2 */ + case 211: + return 158; /* xsr.excsave3 */ + case 212: + return 164; /* xsr.excsave4 */ + case 213: + return 170; /* xsr.excsave5 */ + case 214: + return 176; /* xsr.excsave6 */ + case 215: + return 182; /* xsr.excsave7 */ + case 224: + return 420; /* xsr.cpenable */ + case 228: + return 317; /* xsr.intenable */ + case 230: + return 140; /* xsr.ps */ + case 231: + return 219; /* xsr.vecbase */ + case 232: + return 209; /* xsr.exccause */ + case 233: + return 343; /* xsr.debugcause */ + case 234: + return 358; /* xsr.ccount */ + case 236: + return 346; /* xsr.icount */ + case 237: + return 349; /* xsr.icountlevel */ + case 238: + return 203; /* xsr.excvaddr */ + case 240: + return 361; /* xsr.ccompare0 */ + case 241: + return 364; /* xsr.ccompare1 */ + case 242: + return 367; /* xsr.ccompare2 */ + case 244: + return 212; /* xsr.misc0 */ + case 245: + return 215; /* xsr.misc1 */ + } + break; + case 8: + return 108; /* src */ + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return 109; /* srl */ + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return 107; /* sll */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return 110; /* sra */ + break; + case 12: + return 290; /* mul16u */ + case 13: + return 291; /* mul16s */ + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 374; /* lict */ + case 1: + return 376; /* sict */ + case 2: + return 375; /* licw */ + case 3: + return 377; /* sicw */ + case 8: + return 392; /* ldct */ + case 9: + return 391; /* sdct */ + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return 353; /* rfdo */ + if (Field_t_Slot_inst_get (insn) == 1) + return 354; /* rfdd */ + break; + case 15: + return 415; /* ldpte */ + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 8: + return 439; /* mull */ + case 12: + return 435; /* quou */ + case 13: + return 436; /* quos */ + case 14: + return 437; /* remu */ + case 15: + return 438; /* rems */ + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 127; /* rsr.lbeg */ + case 1: + return 121; /* rsr.lend */ + case 2: + return 124; /* rsr.lcount */ + case 3: + return 130; /* rsr.sar */ + case 5: + return 133; /* rsr.litbase */ + case 12: + return 432; /* rsr.scompare1 */ + case 16: + return 304; /* rsr.acclo */ + case 17: + return 307; /* rsr.acchi */ + case 32: + return 292; /* rsr.m0 */ + case 33: + return 295; /* rsr.m1 */ + case 34: + return 298; /* rsr.m2 */ + case 35: + return 301; /* rsr.m3 */ + case 72: + return 20; /* rsr.windowbase */ + case 73: + return 23; /* rsr.windowstart */ + case 83: + return 394; /* rsr.ptevaddr */ + case 90: + return 396; /* rsr.rasid */ + case 91: + return 399; /* rsr.itlbcfg */ + case 92: + return 402; /* rsr.dtlbcfg */ + case 96: + return 338; /* rsr.ibreakenable */ + case 104: + return 350; /* rsr.ddr */ + case 128: + return 332; /* rsr.ibreaka0 */ + case 129: + return 335; /* rsr.ibreaka1 */ + case 144: + return 320; /* rsr.dbreaka0 */ + case 145: + return 326; /* rsr.dbreaka1 */ + case 160: + return 323; /* rsr.dbreakc0 */ + case 161: + return 329; /* rsr.dbreakc1 */ + case 176: + return 136; /* rsr.176 */ + case 177: + return 141; /* rsr.epc1 */ + case 178: + return 147; /* rsr.epc2 */ + case 179: + return 153; /* rsr.epc3 */ + case 180: + return 159; /* rsr.epc4 */ + case 181: + return 165; /* rsr.epc5 */ + case 182: + return 171; /* rsr.epc6 */ + case 183: + return 177; /* rsr.epc7 */ + case 192: + return 204; /* rsr.depc */ + case 194: + return 183; /* rsr.eps2 */ + case 195: + return 186; /* rsr.eps3 */ + case 196: + return 189; /* rsr.eps4 */ + case 197: + return 192; /* rsr.eps5 */ + case 198: + return 195; /* rsr.eps6 */ + case 199: + return 198; /* rsr.eps7 */ + case 208: + return 137; /* rsr.208 */ + case 209: + return 144; /* rsr.excsave1 */ + case 210: + return 150; /* rsr.excsave2 */ + case 211: + return 156; /* rsr.excsave3 */ + case 212: + return 162; /* rsr.excsave4 */ + case 213: + return 168; /* rsr.excsave5 */ + case 214: + return 174; /* rsr.excsave6 */ + case 215: + return 180; /* rsr.excsave7 */ + case 224: + return 418; /* rsr.cpenable */ + case 226: + return 312; /* rsr.interrupt */ + case 228: + return 315; /* rsr.intenable */ + case 230: + return 138; /* rsr.ps */ + case 231: + return 217; /* rsr.vecbase */ + case 232: + return 207; /* rsr.exccause */ + case 233: + return 341; /* rsr.debugcause */ + case 234: + return 356; /* rsr.ccount */ + case 235: + return 216; /* rsr.prid */ + case 236: + return 344; /* rsr.icount */ + case 237: + return 347; /* rsr.icountlevel */ + case 238: + return 201; /* rsr.excvaddr */ + case 240: + return 359; /* rsr.ccompare0 */ + case 241: + return 362; /* rsr.ccompare1 */ + case 242: + return 365; /* rsr.ccompare2 */ + case 244: + return 210; /* rsr.misc0 */ + case 245: + return 213; /* rsr.misc1 */ + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 128; /* wsr.lbeg */ + case 1: + return 122; /* wsr.lend */ + case 2: + return 125; /* wsr.lcount */ + case 3: + return 131; /* wsr.sar */ + case 5: + return 134; /* wsr.litbase */ + case 12: + return 433; /* wsr.scompare1 */ + case 16: + return 305; /* wsr.acclo */ + case 17: + return 308; /* wsr.acchi */ + case 32: + return 293; /* wsr.m0 */ + case 33: + return 296; /* wsr.m1 */ + case 34: + return 299; /* wsr.m2 */ + case 35: + return 302; /* wsr.m3 */ + case 72: + return 21; /* wsr.windowbase */ + case 73: + return 24; /* wsr.windowstart */ + case 83: + return 393; /* wsr.ptevaddr */ + case 89: + return 355; /* wsr.mmid */ + case 90: + return 397; /* wsr.rasid */ + case 91: + return 400; /* wsr.itlbcfg */ + case 92: + return 403; /* wsr.dtlbcfg */ + case 96: + return 339; /* wsr.ibreakenable */ + case 104: + return 351; /* wsr.ddr */ + case 128: + return 333; /* wsr.ibreaka0 */ + case 129: + return 336; /* wsr.ibreaka1 */ + case 144: + return 321; /* wsr.dbreaka0 */ + case 145: + return 327; /* wsr.dbreaka1 */ + case 160: + return 324; /* wsr.dbreakc0 */ + case 161: + return 330; /* wsr.dbreakc1 */ + case 177: + return 142; /* wsr.epc1 */ + case 178: + return 148; /* wsr.epc2 */ + case 179: + return 154; /* wsr.epc3 */ + case 180: + return 160; /* wsr.epc4 */ + case 181: + return 166; /* wsr.epc5 */ + case 182: + return 172; /* wsr.epc6 */ + case 183: + return 178; /* wsr.epc7 */ + case 192: + return 205; /* wsr.depc */ + case 194: + return 184; /* wsr.eps2 */ + case 195: + return 187; /* wsr.eps3 */ + case 196: + return 190; /* wsr.eps4 */ + case 197: + return 193; /* wsr.eps5 */ + case 198: + return 196; /* wsr.eps6 */ + case 199: + return 199; /* wsr.eps7 */ + case 209: + return 145; /* wsr.excsave1 */ + case 210: + return 151; /* wsr.excsave2 */ + case 211: + return 157; /* wsr.excsave3 */ + case 212: + return 163; /* wsr.excsave4 */ + case 213: + return 169; /* wsr.excsave5 */ + case 214: + return 175; /* wsr.excsave6 */ + case 215: + return 181; /* wsr.excsave7 */ + case 224: + return 419; /* wsr.cpenable */ + case 226: + return 313; /* wsr.intset */ + case 227: + return 314; /* wsr.intclear */ + case 228: + return 316; /* wsr.intenable */ + case 230: + return 139; /* wsr.ps */ + case 231: + return 218; /* wsr.vecbase */ + case 232: + return 208; /* wsr.exccause */ + case 233: + return 342; /* wsr.debugcause */ + case 234: + return 357; /* wsr.ccount */ + case 236: + return 345; /* wsr.icount */ + case 237: + return 348; /* wsr.icountlevel */ + case 238: + return 202; /* wsr.excvaddr */ + case 240: + return 360; /* wsr.ccompare0 */ + case 241: + return 363; /* wsr.ccompare1 */ + case 242: + return 366; /* wsr.ccompare2 */ + case 244: + return 211; /* wsr.misc0 */ + case 245: + return 214; /* wsr.misc1 */ + } + break; + case 2: + return 428; /* sext */ + case 3: + return 421; /* clamps */ + case 4: + return 422; /* min */ + case 5: + return 423; /* max */ + case 6: + return 424; /* minu */ + case 7: + return 425; /* maxu */ + case 8: + return 91; /* moveqz */ + case 9: + return 92; /* movnez */ + case 10: + return 93; /* movltz */ + case 11: + return 94; /* movgez */ + case 14: + switch (Field_st_Slot_inst_get (insn)) + { + case 230: + return 440; /* rur.expstate */ + case 231: + return 37; /* rur.threadptr */ + } + break; + case 15: + switch (Field_sr_Slot_inst_get (insn)) + { + case 230: + return 441; /* wur.expstate */ + case 231: + return 38; /* wur.threadptr */ + } + break; + } + break; + case 4: + case 5: + return 78; /* extui */ + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return 18; /* l32e */ + case 4: + return 19; /* s32e */ + } + break; + } + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 442; /* read_impwire */ + break; + case 1: + if (Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 443; /* setb_expstate */ + if (Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 444; /* clrb_expstate */ + break; + case 2: + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 445; /* wrmsk_expstate */ + break; + } + break; + case 1: + return 85; /* l32r */ + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 86; /* l8ui */ + case 1: + return 82; /* l16ui */ + case 2: + return 84; /* l32i */ + case 4: + return 101; /* s8i */ + case 5: + return 99; /* s16i */ + case 6: + return 100; /* s32i */ + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 384; /* dpfr */ + case 1: + return 385; /* dpfw */ + case 2: + return 386; /* dpfro */ + case 3: + return 387; /* dpfwo */ + case 4: + return 378; /* dhwb */ + case 5: + return 379; /* dhwbi */ + case 6: + return 382; /* dhi */ + case 7: + return 383; /* dii */ + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return 388; /* dpfl */ + case 2: + return 389; /* dhu */ + case 3: + return 390; /* diu */ + case 4: + return 380; /* diwb */ + case 5: + return 381; /* diwbi */ + } + break; + case 12: + return 368; /* ipf */ + case 13: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return 370; /* ipfl */ + case 2: + return 371; /* ihu */ + case 3: + return 372; /* iiu */ + } + break; + case 14: + return 369; /* ihi */ + case 15: + return 373; /* iii */ + } + break; + case 9: + return 83; /* l16si */ + case 10: + return 90; /* movi */ + case 11: + return 429; /* l32ai */ + case 12: + return 39; /* addi */ + case 13: + return 40; /* addmi */ + case 14: + return 431; /* s32c1i */ + case 15: + return 430; /* s32ri */ + } + break; + case 4: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 281; /* mula.dd.ll.ldinc */ + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 283; /* mula.dd.hl.ldinc */ + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 285; /* mula.dd.lh.ldinc */ + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 287; /* mula.dd.hh.ldinc */ + break; + } + break; + case 1: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 280; /* mula.dd.ll.lddec */ + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 282; /* mula.dd.hl.lddec */ + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 284; /* mula.dd.lh.lddec */ + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 286; /* mula.dd.hh.lddec */ + break; + } + break; + case 2: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 236; /* mul.dd.ll */ + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 237; /* mul.dd.hl */ + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 238; /* mul.dd.lh */ + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 239; /* mul.dd.hh */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 264; /* mula.dd.ll */ + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 265; /* mula.dd.hl */ + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 266; /* mula.dd.lh */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 267; /* mula.dd.hh */ + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 268; /* muls.dd.ll */ + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 269; /* muls.dd.hl */ + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 270; /* muls.dd.lh */ + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 271; /* muls.dd.hh */ + break; + } + break; + case 3: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 228; /* mul.ad.ll */ + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 229; /* mul.ad.hl */ + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 230; /* mul.ad.lh */ + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 231; /* mul.ad.hh */ + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 248; /* mula.ad.ll */ + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 249; /* mula.ad.hl */ + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 250; /* mula.ad.lh */ + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 251; /* mula.ad.hh */ + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 252; /* muls.ad.ll */ + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 253; /* muls.ad.hl */ + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 254; /* muls.ad.lh */ + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 255; /* muls.ad.hh */ + break; + } + break; + case 4: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return 273; /* mula.da.ll.ldinc */ + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return 275; /* mula.da.hl.ldinc */ + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return 277; /* mula.da.lh.ldinc */ + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return 279; /* mula.da.hh.ldinc */ + break; + } + break; + case 5: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return 272; /* mula.da.ll.lddec */ + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return 274; /* mula.da.hl.lddec */ + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return 276; /* mula.da.lh.lddec */ + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return 278; /* mula.da.hh.lddec */ + break; + } + break; + case 6: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 232; /* mul.da.ll */ + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 233; /* mul.da.hl */ + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 234; /* mul.da.lh */ + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 235; /* mul.da.hh */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 256; /* mula.da.ll */ + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 257; /* mula.da.hl */ + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 258; /* mula.da.lh */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 259; /* mula.da.hh */ + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 260; /* muls.da.ll */ + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 261; /* muls.da.hl */ + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 262; /* muls.da.lh */ + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 263; /* muls.da.hh */ + break; + } + break; + case 7: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + if (Field_r_Slot_inst_get (insn) == 0) + return 224; /* umul.aa.ll */ + break; + case 1: + if (Field_r_Slot_inst_get (insn) == 0) + return 225; /* umul.aa.hl */ + break; + case 2: + if (Field_r_Slot_inst_get (insn) == 0) + return 226; /* umul.aa.lh */ + break; + case 3: + if (Field_r_Slot_inst_get (insn) == 0) + return 227; /* umul.aa.hh */ + break; + case 4: + if (Field_r_Slot_inst_get (insn) == 0) + return 220; /* mul.aa.ll */ + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0) + return 221; /* mul.aa.hl */ + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0) + return 222; /* mul.aa.lh */ + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0) + return 223; /* mul.aa.hh */ + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0) + return 240; /* mula.aa.ll */ + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0) + return 241; /* mula.aa.hl */ + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0) + return 242; /* mula.aa.lh */ + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0) + return 243; /* mula.aa.hh */ + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0) + return 244; /* muls.aa.ll */ + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0) + return 245; /* muls.aa.hl */ + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0) + return 246; /* muls.aa.lh */ + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0) + return 247; /* muls.aa.hh */ + break; + } + break; + case 8: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return 289; /* ldinc */ + break; + case 9: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return 288; /* lddec */ + break; + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 76; /* call0 */ + case 1: + return 7; /* call4 */ + case 2: + return 6; /* call8 */ + case 3: + return 5; /* call12 */ + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 80; /* j */ + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 72; /* beqz */ + case 1: + return 73; /* bnez */ + case 2: + return 75; /* bltz */ + case 3: + return 74; /* bgez */ + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 52; /* beqi */ + case 1: + return 53; /* bnei */ + case 2: + return 55; /* blti */ + case 3: + return 54; /* bgei */ + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 11; /* entry */ + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return 87; /* loop */ + case 9: + return 88; /* loopnez */ + case 10: + return 89; /* loopgtz */ + } + break; + case 2: + return 59; /* bltui */ + case 3: + return 58; /* bgeui */ + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 67; /* bnone */ + case 1: + return 60; /* beq */ + case 2: + return 63; /* blt */ + case 3: + return 65; /* bltu */ + case 4: + return 68; /* ball */ + case 5: + return 70; /* bbc */ + case 6: + case 7: + return 56; /* bbci */ + case 8: + return 66; /* bany */ + case 9: + return 61; /* bne */ + case 10: + return 62; /* bge */ + case 11: + return 64; /* bgeu */ + case 12: + return 69; /* bnall */ + case 13: + return 71; /* bbs */ + case 14: + case 15: + return 57; /* bbsi */ + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return 33; /* movi.n */ + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return 28; /* beqz.n */ + case 1: + return 29; /* bnez.n */ + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return 32; /* mov.n */ + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return 35; /* ret.n */ + case 1: + return 15; /* retw.n */ + case 2: + return 319; /* break.n */ + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 34; /* nop.n */ + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return 31; /* l32i.n */ + case 9: + return 36; /* s32i.n */ + case 10: + return 26; /* add.n */ + case 11: + return 27; /* addi.n */ + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = insn[0] & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 56 /* num_fields */, + 93, operands, + 320, iclasses, + 446, opcodes, 0, + 2, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c index 40475e5..00301c2 100644 --- a/target/xtensa/core-dc233c.c +++ b/target/xtensa/core-dc233c.c @@ -35,6 +35,9 @@ #include "core-dc233c/core-isa.h" #include "overlay_tool.h" +#define xtensa_modules xtensa_modules_dc233c +#include "core-dc233c/xtensa-modules.c" + static XtensaConfig dc233c __attribute__((unused)) = { .name = "dc233c", .gdb_regmap = { @@ -44,6 +47,7 @@ static XtensaConfig dc233c __attribute__((unused)) = { #include "core-dc233c/gdb-config.c" } }, + .isa_internal = &xtensa_modules, .clock_freq_khz = 10000, DEFAULT_SECTIONS }; diff --git a/target/xtensa/core-dc233c/xtensa-modules.c b/target/xtensa/core-dc233c/xtensa-modules.c new file mode 100644 index 0000000..2728311 --- /dev/null +++ b/target/xtensa/core-dc233c/xtensa-modules.c @@ -0,0 +1,15232 @@ +/* Xtensa configuration-specific ISA information. + + Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include <xtensa-isa.h> +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 71 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID6", 1, 0 }, + { "INSTPGSZID5", 1, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID6", 1, 0 }, + { "DATAPGSZID5", 1, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 78 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_LITBADDR, + STATE_LITBEN, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_ASID3, + STATE_ASID2, + STATE_ASID1, + STATE_INSTPGSZID6, + STATE_INSTPGSZID5, + STATE_INSTPGSZID4, + STATE_DATAPGSZID6, + STATE_DATAPGSZID5, + STATE_DATAPGSZID4, + STATE_PTBASE, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3 +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mx_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_my_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +Operand_my_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mw_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr1_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr2_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr3_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3) != 0; + return error; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static int +Operand_tp7_decode (uint32 *valp) +{ + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; +} + +static int +Operand_tp7_encode (uint32 *valp) +{ + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; +} + +static int +Operand_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; +} + +static int +Operand_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_mx_encode, Operand_mx_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_my_encode, Operand_my_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_mw_encode, Operand_mw_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr0_encode, Operand_mr0_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr1_encode, Operand_mr1_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr2_encode, Operand_mr2_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr3_encode, Operand_mr3_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_immt, + OPERAND_imms, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_t, + OPERAND_bbi4, + OPERAND_bbi, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sae, + OPERAND_sal, + OPERAND_sargt, + OPERAND_sas4, + OPERAND_sas, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_bitindex, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'i' }, + { { STATE_INSTPGSZID5 }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'o' }, + { { STATE_INSTPGSZID5 }, 'o' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'm' }, + { { STATE_INSTPGSZID5 }, 'm' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'i' }, + { { STATE_DATAPGSZID5 }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'o' }, + { { STATE_DATAPGSZID5 }, 'o' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'm' }, + { { STATE_DATAPGSZID5 }, 'm' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_176_args, + 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rer */, + 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_wer */, + 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_176, + ICLASS_xt_iclass_wsr_176, + ICLASS_xt_iclass_rsr_208, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_wsr_ptevaddr, + ICLASS_xt_iclass_rsr_ptevaddr, + ICLASS_xt_iclass_xsr_ptevaddr, + ICLASS_xt_iclass_rsr_rasid, + ICLASS_xt_iclass_wsr_rasid, + ICLASS_xt_iclass_xsr_rasid, + ICLASS_xt_iclass_rsr_itlbcfg, + ICLASS_xt_iclass_wsr_itlbcfg, + ICLASS_xt_iclass_xsr_itlbcfg, + ICLASS_xt_iclass_rsr_dtlbcfg, + ICLASS_xt_iclass_wsr_dtlbcfg, + ICLASS_xt_iclass_xsr_dtlbcfg, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_ldpte, + ICLASS_xt_iclass_hwwitlba, + ICLASS_xt_iclass_hwwdtlba, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { + Opcode_wsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", ICLASS_xt_iclass_rsr_176, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "wsr.176", ICLASS_xt_iclass_wsr_176, + 0, + Opcode_wsr_176_encode_fns, 0, 0 }, + { "rsr.208", ICLASS_xt_iclass_rsr_208, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", ICLASS_xt_iclass_ldpte, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", ICLASS_xt_iclass_hwwitlba, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_SIMCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_176, + OPCODE_WSR_176, + OPCODE_RSR_208, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MUL_AA_LL, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_HH, + OPCODE_UMUL_AA_LL, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_HH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_HH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DD_LL, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_HH, + OPCODE_MULA_AA_LL, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_HH, + OPCODE_MULS_AA_LL, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_HH, + OPCODE_MULA_AD_LL, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_HH, + OPCODE_MULS_AD_LL, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_HH, + OPCODE_MULA_DA_LL, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_HH, + OPCODE_MULS_DA_LL, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_HH, + OPCODE_MULA_DD_LL, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_HH, + OPCODE_MULS_DD_LL, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_HH, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_DPFL, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_WSR_PTEVADDR, + OPCODE_RSR_PTEVADDR, + OPCODE_XSR_PTEVADDR, + OPCODE_RSR_RASID, + OPCODE_WSR_RASID, + OPCODE_XSR_RASID, + OPCODE_RSR_ITLBCFG, + OPCODE_WSR_ITLBCFG, + OPCODE_XSR_ITLBCFG, + OPCODE_RSR_DTLBCFG, + OPCODE_WSR_DTLBCFG, + OPCODE_XSR_DTLBCFG, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_LDPTE, + OPCODE_HWWITLBA, + OPCODE_HWWDTLBA, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RET; + case 1: + return OPCODE_RETW; + case 2: + return OPCODE_JX; + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALLX0; + case 1: + return OPCODE_CALLX4; + case 2: + return OPCODE_CALLX8; + case 3: + return OPCODE_CALLX12; + } + break; + } + break; + case 1: + return OPCODE_MOVSP; + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ISYNC; + case 1: + return OPCODE_RSYNC; + case 2: + return OPCODE_ESYNC; + case 3: + return OPCODE_DSYNC; + case 8: + return OPCODE_EXCW; + case 12: + return OPCODE_MEMW; + case 13: + return OPCODE_EXTW; + case 15: + return OPCODE_NOP; + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RFE; + case 2: + return OPCODE_RFDE; + case 4: + return OPCODE_RFWO; + case 5: + return OPCODE_RFWU; + } + break; + case 1: + return OPCODE_RFI; + } + break; + case 4: + return OPCODE_BREAK; + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + break; + } + break; + case 6: + return OPCODE_RSIL; + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + break; + } + break; + case 1: + return OPCODE_AND; + case 2: + return OPCODE_OR; + case 3: + return OPCODE_XOR; + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + break; + case 6: + return OPCODE_RER; + case 7: + return OPCODE_WER; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + break; + case 14: + return OPCODE_NSA; + case 15: + return OPCODE_NSAU; + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return OPCODE_HWWITLBA; + case 3: + return OPCODE_RITLB0; + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + break; + case 5: + return OPCODE_PITLB; + case 6: + return OPCODE_WITLB; + case 7: + return OPCODE_RITLB1; + case 9: + return OPCODE_HWWDTLBA; + case 11: + return OPCODE_RDTLB0; + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + break; + case 13: + return OPCODE_PDTLB; + case 14: + return OPCODE_WDTLB; + case 15: + return OPCODE_RDTLB1; + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_NEG; + case 1: + return OPCODE_ABS; + } + break; + case 8: + return OPCODE_ADD; + case 9: + return OPCODE_ADDX2; + case 10: + return OPCODE_ADDX4; + case 11: + return OPCODE_ADDX8; + case 12: + return OPCODE_SUB; + case 13: + return OPCODE_SUBX2; + case 14: + return OPCODE_SUBX4; + case 15: + return OPCODE_SUBX8; + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return OPCODE_SLLI; + case 2: + case 3: + return OPCODE_SRAI; + case 4: + return OPCODE_SRLI; + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_XSR_LBEG; + case 1: + return OPCODE_XSR_LEND; + case 2: + return OPCODE_XSR_LCOUNT; + case 3: + return OPCODE_XSR_SAR; + case 5: + return OPCODE_XSR_LITBASE; + case 12: + return OPCODE_XSR_SCOMPARE1; + case 16: + return OPCODE_XSR_ACCLO; + case 17: + return OPCODE_XSR_ACCHI; + case 32: + return OPCODE_XSR_M0; + case 33: + return OPCODE_XSR_M1; + case 34: + return OPCODE_XSR_M2; + case 35: + return OPCODE_XSR_M3; + case 72: + return OPCODE_XSR_WINDOWBASE; + case 73: + return OPCODE_XSR_WINDOWSTART; + case 83: + return OPCODE_XSR_PTEVADDR; + case 90: + return OPCODE_XSR_RASID; + case 91: + return OPCODE_XSR_ITLBCFG; + case 92: + return OPCODE_XSR_DTLBCFG; + case 96: + return OPCODE_XSR_IBREAKENABLE; + case 99: + return OPCODE_XSR_ATOMCTL; + case 104: + return OPCODE_XSR_DDR; + case 128: + return OPCODE_XSR_IBREAKA0; + case 129: + return OPCODE_XSR_IBREAKA1; + case 144: + return OPCODE_XSR_DBREAKA0; + case 145: + return OPCODE_XSR_DBREAKA1; + case 160: + return OPCODE_XSR_DBREAKC0; + case 161: + return OPCODE_XSR_DBREAKC1; + case 177: + return OPCODE_XSR_EPC1; + case 178: + return OPCODE_XSR_EPC2; + case 179: + return OPCODE_XSR_EPC3; + case 180: + return OPCODE_XSR_EPC4; + case 181: + return OPCODE_XSR_EPC5; + case 182: + return OPCODE_XSR_EPC6; + case 183: + return OPCODE_XSR_EPC7; + case 192: + return OPCODE_XSR_DEPC; + case 194: + return OPCODE_XSR_EPS2; + case 195: + return OPCODE_XSR_EPS3; + case 196: + return OPCODE_XSR_EPS4; + case 197: + return OPCODE_XSR_EPS5; + case 198: + return OPCODE_XSR_EPS6; + case 199: + return OPCODE_XSR_EPS7; + case 209: + return OPCODE_XSR_EXCSAVE1; + case 210: + return OPCODE_XSR_EXCSAVE2; + case 211: + return OPCODE_XSR_EXCSAVE3; + case 212: + return OPCODE_XSR_EXCSAVE4; + case 213: + return OPCODE_XSR_EXCSAVE5; + case 214: + return OPCODE_XSR_EXCSAVE6; + case 215: + return OPCODE_XSR_EXCSAVE7; + case 224: + return OPCODE_XSR_CPENABLE; + case 228: + return OPCODE_XSR_INTENABLE; + case 230: + return OPCODE_XSR_PS; + case 231: + return OPCODE_XSR_VECBASE; + case 232: + return OPCODE_XSR_EXCCAUSE; + case 233: + return OPCODE_XSR_DEBUGCAUSE; + case 234: + return OPCODE_XSR_CCOUNT; + case 236: + return OPCODE_XSR_ICOUNT; + case 237: + return OPCODE_XSR_ICOUNTLEVEL; + case 238: + return OPCODE_XSR_EXCVADDR; + case 240: + return OPCODE_XSR_CCOMPARE0; + case 241: + return OPCODE_XSR_CCOMPARE1; + case 242: + return OPCODE_XSR_CCOMPARE2; + case 244: + return OPCODE_XSR_MISC0; + case 245: + return OPCODE_XSR_MISC1; + } + break; + case 8: + return OPCODE_SRC; + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + break; + case 12: + return OPCODE_MUL16U; + case 13: + return OPCODE_MUL16S; + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_LICT; + case 1: + return OPCODE_SICT; + case 2: + return OPCODE_LICW; + case 3: + return OPCODE_SICW; + case 8: + return OPCODE_LDCT; + case 9: + return OPCODE_SDCT; + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + break; + case 15: + return OPCODE_LDPTE; + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 8: + return OPCODE_MULL; + case 12: + return OPCODE_QUOU; + case 13: + return OPCODE_QUOS; + case 14: + return OPCODE_REMU; + case 15: + return OPCODE_REMS; + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RSR_LBEG; + case 1: + return OPCODE_RSR_LEND; + case 2: + return OPCODE_RSR_LCOUNT; + case 3: + return OPCODE_RSR_SAR; + case 5: + return OPCODE_RSR_LITBASE; + case 12: + return OPCODE_RSR_SCOMPARE1; + case 16: + return OPCODE_RSR_ACCLO; + case 17: + return OPCODE_RSR_ACCHI; + case 32: + return OPCODE_RSR_M0; + case 33: + return OPCODE_RSR_M1; + case 34: + return OPCODE_RSR_M2; + case 35: + return OPCODE_RSR_M3; + case 72: + return OPCODE_RSR_WINDOWBASE; + case 73: + return OPCODE_RSR_WINDOWSTART; + case 83: + return OPCODE_RSR_PTEVADDR; + case 90: + return OPCODE_RSR_RASID; + case 91: + return OPCODE_RSR_ITLBCFG; + case 92: + return OPCODE_RSR_DTLBCFG; + case 96: + return OPCODE_RSR_IBREAKENABLE; + case 99: + return OPCODE_RSR_ATOMCTL; + case 104: + return OPCODE_RSR_DDR; + case 128: + return OPCODE_RSR_IBREAKA0; + case 129: + return OPCODE_RSR_IBREAKA1; + case 144: + return OPCODE_RSR_DBREAKA0; + case 145: + return OPCODE_RSR_DBREAKA1; + case 160: + return OPCODE_RSR_DBREAKC0; + case 161: + return OPCODE_RSR_DBREAKC1; + case 176: + return OPCODE_RSR_176; + case 177: + return OPCODE_RSR_EPC1; + case 178: + return OPCODE_RSR_EPC2; + case 179: + return OPCODE_RSR_EPC3; + case 180: + return OPCODE_RSR_EPC4; + case 181: + return OPCODE_RSR_EPC5; + case 182: + return OPCODE_RSR_EPC6; + case 183: + return OPCODE_RSR_EPC7; + case 192: + return OPCODE_RSR_DEPC; + case 194: + return OPCODE_RSR_EPS2; + case 195: + return OPCODE_RSR_EPS3; + case 196: + return OPCODE_RSR_EPS4; + case 197: + return OPCODE_RSR_EPS5; + case 198: + return OPCODE_RSR_EPS6; + case 199: + return OPCODE_RSR_EPS7; + case 208: + return OPCODE_RSR_208; + case 209: + return OPCODE_RSR_EXCSAVE1; + case 210: + return OPCODE_RSR_EXCSAVE2; + case 211: + return OPCODE_RSR_EXCSAVE3; + case 212: + return OPCODE_RSR_EXCSAVE4; + case 213: + return OPCODE_RSR_EXCSAVE5; + case 214: + return OPCODE_RSR_EXCSAVE6; + case 215: + return OPCODE_RSR_EXCSAVE7; + case 224: + return OPCODE_RSR_CPENABLE; + case 226: + return OPCODE_RSR_INTERRUPT; + case 228: + return OPCODE_RSR_INTENABLE; + case 230: + return OPCODE_RSR_PS; + case 231: + return OPCODE_RSR_VECBASE; + case 232: + return OPCODE_RSR_EXCCAUSE; + case 233: + return OPCODE_RSR_DEBUGCAUSE; + case 234: + return OPCODE_RSR_CCOUNT; + case 235: + return OPCODE_RSR_PRID; + case 236: + return OPCODE_RSR_ICOUNT; + case 237: + return OPCODE_RSR_ICOUNTLEVEL; + case 238: + return OPCODE_RSR_EXCVADDR; + case 240: + return OPCODE_RSR_CCOMPARE0; + case 241: + return OPCODE_RSR_CCOMPARE1; + case 242: + return OPCODE_RSR_CCOMPARE2; + case 244: + return OPCODE_RSR_MISC0; + case 245: + return OPCODE_RSR_MISC1; + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_WSR_LBEG; + case 1: + return OPCODE_WSR_LEND; + case 2: + return OPCODE_WSR_LCOUNT; + case 3: + return OPCODE_WSR_SAR; + case 5: + return OPCODE_WSR_LITBASE; + case 12: + return OPCODE_WSR_SCOMPARE1; + case 16: + return OPCODE_WSR_ACCLO; + case 17: + return OPCODE_WSR_ACCHI; + case 32: + return OPCODE_WSR_M0; + case 33: + return OPCODE_WSR_M1; + case 34: + return OPCODE_WSR_M2; + case 35: + return OPCODE_WSR_M3; + case 72: + return OPCODE_WSR_WINDOWBASE; + case 73: + return OPCODE_WSR_WINDOWSTART; + case 83: + return OPCODE_WSR_PTEVADDR; + case 89: + return OPCODE_WSR_MMID; + case 90: + return OPCODE_WSR_RASID; + case 91: + return OPCODE_WSR_ITLBCFG; + case 92: + return OPCODE_WSR_DTLBCFG; + case 96: + return OPCODE_WSR_IBREAKENABLE; + case 99: + return OPCODE_WSR_ATOMCTL; + case 104: + return OPCODE_WSR_DDR; + case 128: + return OPCODE_WSR_IBREAKA0; + case 129: + return OPCODE_WSR_IBREAKA1; + case 144: + return OPCODE_WSR_DBREAKA0; + case 145: + return OPCODE_WSR_DBREAKA1; + case 160: + return OPCODE_WSR_DBREAKC0; + case 161: + return OPCODE_WSR_DBREAKC1; + case 176: + return OPCODE_WSR_176; + case 177: + return OPCODE_WSR_EPC1; + case 178: + return OPCODE_WSR_EPC2; + case 179: + return OPCODE_WSR_EPC3; + case 180: + return OPCODE_WSR_EPC4; + case 181: + return OPCODE_WSR_EPC5; + case 182: + return OPCODE_WSR_EPC6; + case 183: + return OPCODE_WSR_EPC7; + case 192: + return OPCODE_WSR_DEPC; + case 194: + return OPCODE_WSR_EPS2; + case 195: + return OPCODE_WSR_EPS3; + case 196: + return OPCODE_WSR_EPS4; + case 197: + return OPCODE_WSR_EPS5; + case 198: + return OPCODE_WSR_EPS6; + case 199: + return OPCODE_WSR_EPS7; + case 209: + return OPCODE_WSR_EXCSAVE1; + case 210: + return OPCODE_WSR_EXCSAVE2; + case 211: + return OPCODE_WSR_EXCSAVE3; + case 212: + return OPCODE_WSR_EXCSAVE4; + case 213: + return OPCODE_WSR_EXCSAVE5; + case 214: + return OPCODE_WSR_EXCSAVE6; + case 215: + return OPCODE_WSR_EXCSAVE7; + case 224: + return OPCODE_WSR_CPENABLE; + case 226: + return OPCODE_WSR_INTSET; + case 227: + return OPCODE_WSR_INTCLEAR; + case 228: + return OPCODE_WSR_INTENABLE; + case 230: + return OPCODE_WSR_PS; + case 231: + return OPCODE_WSR_VECBASE; + case 232: + return OPCODE_WSR_EXCCAUSE; + case 233: + return OPCODE_WSR_DEBUGCAUSE; + case 234: + return OPCODE_WSR_CCOUNT; + case 236: + return OPCODE_WSR_ICOUNT; + case 237: + return OPCODE_WSR_ICOUNTLEVEL; + case 238: + return OPCODE_WSR_EXCVADDR; + case 240: + return OPCODE_WSR_CCOMPARE0; + case 241: + return OPCODE_WSR_CCOMPARE1; + case 242: + return OPCODE_WSR_CCOMPARE2; + case 244: + return OPCODE_WSR_MISC0; + case 245: + return OPCODE_WSR_MISC1; + } + break; + case 2: + return OPCODE_SEXT; + case 3: + return OPCODE_CLAMPS; + case 4: + return OPCODE_MIN; + case 5: + return OPCODE_MAX; + case 6: + return OPCODE_MINU; + case 7: + return OPCODE_MAXU; + case 8: + return OPCODE_MOVEQZ; + case 9: + return OPCODE_MOVNEZ; + case 10: + return OPCODE_MOVLTZ; + case 11: + return OPCODE_MOVGEZ; + case 14: + switch (Field_st_Slot_inst_get (insn)) + { + case 230: + return OPCODE_RUR_EXPSTATE; + case 231: + return OPCODE_RUR_THREADPTR; + } + break; + case 15: + switch (Field_sr_Slot_inst_get (insn)) + { + case 230: + return OPCODE_WUR_EXPSTATE; + case 231: + return OPCODE_WUR_THREADPTR; + } + break; + } + break; + case 4: + case 5: + return OPCODE_EXTUI; + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L32E; + case 4: + return OPCODE_S32E; + } + break; + } + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + break; + case 1: + if (Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + break; + case 2: + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + break; + } + break; + case 1: + return OPCODE_L32R; + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L8UI; + case 1: + return OPCODE_L16UI; + case 2: + return OPCODE_L32I; + case 4: + return OPCODE_S8I; + case 5: + return OPCODE_S16I; + case 6: + return OPCODE_S32I; + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFR; + case 1: + return OPCODE_DPFW; + case 2: + return OPCODE_DPFRO; + case 3: + return OPCODE_DPFWO; + case 4: + return OPCODE_DHWB; + case 5: + return OPCODE_DHWBI; + case 6: + return OPCODE_DHI; + case 7: + return OPCODE_DII; + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFL; + case 2: + return OPCODE_DHU; + case 3: + return OPCODE_DIU; + case 4: + return OPCODE_DIWB; + case 5: + return OPCODE_DIWBI; + } + break; + case 12: + return OPCODE_IPF; + case 13: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_IPFL; + case 2: + return OPCODE_IHU; + case 3: + return OPCODE_IIU; + } + break; + case 14: + return OPCODE_IHI; + case 15: + return OPCODE_III; + } + break; + case 9: + return OPCODE_L16SI; + case 10: + return OPCODE_MOVI; + case 11: + return OPCODE_L32AI; + case 12: + return OPCODE_ADDI; + case 13: + return OPCODE_ADDMI; + case 14: + return OPCODE_S32C1I; + case 15: + return OPCODE_S32RI; + } + break; + case 4: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + break; + } + break; + case 1: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + break; + } + break; + case 2: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + break; + } + break; + case 3: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + break; + } + break; + case 4: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + break; + } + break; + case 5: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + break; + } + break; + case 6: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + break; + } + break; + case 7: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + break; + case 1: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + break; + case 2: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + break; + case 3: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + break; + case 4: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + break; + } + break; + case 8: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + break; + case 9: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + break; + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALL0; + case 1: + return OPCODE_CALL4; + case 2: + return OPCODE_CALL8; + case 3: + return OPCODE_CALL12; + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_J; + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQZ; + case 1: + return OPCODE_BNEZ; + case 2: + return OPCODE_BLTZ; + case 3: + return OPCODE_BGEZ; + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQI; + case 1: + return OPCODE_BNEI; + case 2: + return OPCODE_BLTI; + case 3: + return OPCODE_BGEI; + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ENTRY; + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return OPCODE_LOOP; + case 9: + return OPCODE_LOOPNEZ; + case 10: + return OPCODE_LOOPGTZ; + } + break; + case 2: + return OPCODE_BLTUI; + case 3: + return OPCODE_BGEUI; + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BNONE; + case 1: + return OPCODE_BEQ; + case 2: + return OPCODE_BLT; + case 3: + return OPCODE_BLTU; + case 4: + return OPCODE_BALL; + case 5: + return OPCODE_BBC; + case 6: + case 7: + return OPCODE_BBCI; + case 8: + return OPCODE_BANY; + case 9: + return OPCODE_BNE; + case 10: + return OPCODE_BGE; + case 11: + return OPCODE_BGEU; + case 12: + return OPCODE_BNALL; + case 13: + return OPCODE_BBS; + case 14: + case 15: + return OPCODE_BBSI; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOVI_N; + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_BEQZ_N; + case 1: + return OPCODE_BNEZ_N; + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOV_N; + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_RET_N; + case 1: + return OPCODE_RETW_N; + case 2: + return OPCODE_BREAK_N; + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return OPCODE_L32I_N; + case 9: + return OPCODE_S32I_N; + case 10: + return OPCODE_ADD_N; + case 11: + return OPCODE_ADDI_N; + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = insn[0] & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 56 /* num_fields */, + 93, operands, + 326, iclasses, + 452, opcodes, 0, + 2, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c index 15ef470..f41de9a 100644 --- a/target/xtensa/core-fsf.c +++ b/target/xtensa/core-fsf.c @@ -29,11 +29,15 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "qemu-common.h" #include "qemu/host-utils.h" #include "core-fsf/core-isa.h" #include "overlay_tool.h" +#define xtensa_modules xtensa_modules_fsf +#include "core-fsf/xtensa-modules.c" + static XtensaConfig fsf __attribute__((unused)) = { .name = "fsf", .gdb_regmap = { @@ -42,6 +46,7 @@ static XtensaConfig fsf __attribute__((unused)) = { XTREG_END }, }, + .isa_internal = &xtensa_modules, .clock_freq_khz = 10000, DEFAULT_SECTIONS }; diff --git a/target/xtensa/core-fsf/xtensa-modules.c b/target/xtensa/core-fsf/xtensa-modules.c new file mode 100644 index 0000000..238800d --- /dev/null +++ b/target/xtensa/core-fsf/xtensa-modules.c @@ -0,0 +1,9841 @@ +/* Xtensa configuration-specific ISA information. + Copyright 2003, 2004, 2005 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include <xtensa-isa.h> +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "PTEVADDR", 83, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 } +}; + +#define NUM_SYSREGS 49 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 0 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 17, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 17, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 } +}; + +#define NUM_STATES 58 + +/* Macros for xtensa_state numbers (for use in iclasses because the + state numbers are not available when the iclass table is generated). */ + +#define STATE_LCOUNT 0 +#define STATE_PC 1 +#define STATE_ICOUNT 2 +#define STATE_DDR 3 +#define STATE_INTERRUPT 4 +#define STATE_CCOUNT 5 +#define STATE_XTSYNC 6 +#define STATE_EPC1 7 +#define STATE_EPC2 8 +#define STATE_EPC3 9 +#define STATE_EPC4 10 +#define STATE_EXCSAVE1 11 +#define STATE_EXCSAVE2 12 +#define STATE_EXCSAVE3 13 +#define STATE_EXCSAVE4 14 +#define STATE_EPS2 15 +#define STATE_EPS3 16 +#define STATE_EPS4 17 +#define STATE_EXCCAUSE 18 +#define STATE_PSINTLEVEL 19 +#define STATE_PSUM 20 +#define STATE_PSWOE 21 +#define STATE_PSRING 22 +#define STATE_PSEXCM 23 +#define STATE_DEPC 24 +#define STATE_EXCVADDR 25 +#define STATE_WindowBase 26 +#define STATE_WindowStart 27 +#define STATE_PSCALLINC 28 +#define STATE_PSOWB 29 +#define STATE_LBEG 30 +#define STATE_LEND 31 +#define STATE_SAR 32 +#define STATE_LITBADDR 33 +#define STATE_LITBEN 34 +#define STATE_MISC0 35 +#define STATE_MISC1 36 +#define STATE_InOCDMode 37 +#define STATE_INTENABLE 38 +#define STATE_DBREAKA0 39 +#define STATE_DBREAKC0 40 +#define STATE_DBREAKA1 41 +#define STATE_DBREAKC1 42 +#define STATE_IBREAKA0 43 +#define STATE_IBREAKA1 44 +#define STATE_IBREAKENABLE 45 +#define STATE_ICOUNTLEVEL 46 +#define STATE_DEBUGCAUSE 47 +#define STATE_DBNUM 48 +#define STATE_CCOMPARE0 49 +#define STATE_CCOMPARE1 50 +#define STATE_CCOMPARE2 51 +#define STATE_ASID3 52 +#define STATE_ASID2 53 +#define STATE_ASID1 54 +#define STATE_INSTPGSZID4 55 +#define STATE_DATAPGSZID4 56 +#define STATE_PTBASE 57 + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", 0, 32, 64 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3f) != 0; + return error; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3f) != 0; + return error; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3f) != 0; + return error; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3f) != 0; + return error; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x3f) != 0; + return error; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", 3, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", 26, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", 14, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", 0, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", 35, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", 36, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", 37, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", 38, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", 14, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", 14, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", 34, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", 33, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", 0, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", 14, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", 14, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", 4, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", 4, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", 4, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", 13, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", 4, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", 4, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", 6, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", 18, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", 13, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", 3, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", 7, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "immt", 0, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", 5, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, + { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, + { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, + { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, + { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, + { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, + { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, + { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { 11 /* ars_entry */ }, 's' }, + { { 4 /* ars */ }, 'i' }, + { { 1 /* uimm12x8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { 2 /* simm4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 16 /* ai4const */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 15 /* uimm6 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { 4 /* ars */ }, 'o' }, + { { 14 /* simm7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 23 /* simm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 24 /* simm8x256 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 17 /* b4const */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 37 /* bbi */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 18 /* b4constu */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 30 /* label12 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 52 /* sae */ }, 'i' }, + { { 27 /* op2p1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { 31 /* soffset */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { 6 /* art */ }, 'o' }, + { { 32 /* uimm16x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 25 /* simm12b */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { 3 /* arr */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { 56 /* sas */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 26 /* msalp32 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 54 /* sargt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { 6 /* art */ }, 'o' }, + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { 34 /* imms */ }, 'i' }, + { { 33 /* immt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { 34 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdo */, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 } +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80200; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10f; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4830; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4831; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4816; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4930; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4931; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4916; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc00; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60f; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30f; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00f; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200c00; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d00; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700600; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700e00; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700100; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700900; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700a00; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700200; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700b00; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700300; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700800; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700400; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700c00; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700500; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700d00; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200100; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200900; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200200; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0800; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0900; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0a00; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200a00; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1006; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200500; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200600; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200400; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x304; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x331; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x316; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x531; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x516; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb030; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd030; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe630; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe631; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe616; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb130; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb131; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb116; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd130; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd131; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd116; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb230; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb231; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb216; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd230; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd231; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd216; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb330; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb331; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb316; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd330; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd331; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd316; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb430; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb431; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb416; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd430; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd431; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd416; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc230; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc231; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc216; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc330; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc331; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc316; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc430; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc431; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc416; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee30; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee31; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee16; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc030; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc031; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc016; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe830; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe831; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe816; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf430; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf431; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf416; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf530; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf531; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf516; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb30; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe230; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe231; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe331; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe430; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe431; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe416; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20f; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9030; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9031; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9016; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa031; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa016; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9130; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9131; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9116; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa130; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa131; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa116; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8031; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8016; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8131; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8116; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6030; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6031; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6016; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe930; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe931; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe916; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec30; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec31; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec16; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed30; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed31; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed16; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6830; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6831; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1f; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e1f; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea30; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea31; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea16; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf030; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf031; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf016; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf130; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf131; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf116; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf230; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf231; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf216; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0700; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0700; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0700; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31f; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240700; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250700; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280740; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280750; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260700; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270700; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200700; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210700; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220700; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230700; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91f; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5331; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5330; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5316; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a30; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a31; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a16; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b30; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b31; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b16; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c30; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c31; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c16; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc05; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd05; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb05; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf05; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe05; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x405; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x705; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x605; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe04; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf04; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", 0 /* xt_iclass_excw */, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", 1 /* xt_iclass_rfe */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", 2 /* xt_iclass_rfde */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", 3 /* xt_iclass_syscall */, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", 4 /* xt_iclass_simcall */, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", 5 /* xt_iclass_call12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", 6 /* xt_iclass_call8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", 7 /* xt_iclass_call4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", 8 /* xt_iclass_callx12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", 9 /* xt_iclass_callx8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", 10 /* xt_iclass_callx4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", 11 /* xt_iclass_entry */, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", 12 /* xt_iclass_movsp */, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", 13 /* xt_iclass_rotw */, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", 16 /* xt_iclass_l32e */, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", 17 /* xt_iclass_s32e */, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", 24 /* xt_iclass_add.n */, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", 25 /* xt_iclass_addi.n */, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", 27 /* xt_iclass_ill.n */, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", 28 /* xt_iclass_loadi4 */, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", 29 /* xt_iclass_mov.n */, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", 30 /* xt_iclass_movi.n */, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", 31 /* xt_iclass_nopn */, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", 32 /* xt_iclass_retn */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", 33 /* xt_iclass_storei4 */, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "addi", 34 /* xt_iclass_addi */, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", 35 /* xt_iclass_addmi */, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", 36 /* xt_iclass_addsub */, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", 36 /* xt_iclass_addsub */, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", 37 /* xt_iclass_bit */, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", 37 /* xt_iclass_bit */, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", 37 /* xt_iclass_bit */, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", 39 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", 39 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", 40 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", 40 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", 43 /* xt_iclass_call0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", 44 /* xt_iclass_callx0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", 45 /* xt_iclass_exti */, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", 46 /* xt_iclass_ill */, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", 47 /* xt_iclass_jump */, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", 48 /* xt_iclass_jumpx */, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", 49 /* xt_iclass_l16ui */, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", 50 /* xt_iclass_l16si */, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", 51 /* xt_iclass_l32i */, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", 52 /* xt_iclass_l32r */, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", 53 /* xt_iclass_l8i */, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", 54 /* xt_iclass_loop */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", 55 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", 55 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", 56 /* xt_iclass_movi */, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", 57 /* xt_iclass_movz */, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", 57 /* xt_iclass_movz */, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", 57 /* xt_iclass_movz */, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", 57 /* xt_iclass_movz */, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", 58 /* xt_iclass_neg */, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", 58 /* xt_iclass_neg */, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", 59 /* xt_iclass_nop */, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", 60 /* xt_iclass_return */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", 61 /* xt_iclass_s16i */, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", 62 /* xt_iclass_s32i */, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", 63 /* xt_iclass_s8i */, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", 64 /* xt_iclass_sar */, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", 64 /* xt_iclass_sar */, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", 64 /* xt_iclass_sar */, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", 64 /* xt_iclass_sar */, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", 65 /* xt_iclass_sari */, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", 66 /* xt_iclass_shifts */, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", 67 /* xt_iclass_shiftst */, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", 68 /* xt_iclass_shiftt */, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", 68 /* xt_iclass_shiftt */, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", 69 /* xt_iclass_slli */, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", 70 /* xt_iclass_srai */, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", 71 /* xt_iclass_srli */, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", 72 /* xt_iclass_memw */, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", 73 /* xt_iclass_extw */, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", 74 /* xt_iclass_isync */, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", 75 /* xt_iclass_sync */, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", 75 /* xt_iclass_sync */, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", 75 /* xt_iclass_sync */, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", 76 /* xt_iclass_rsil */, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", 77 /* xt_iclass_rsr.lend */, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", 78 /* xt_iclass_wsr.lend */, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", 79 /* xt_iclass_xsr.lend */, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", 86 /* xt_iclass_rsr.sar */, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", 87 /* xt_iclass_wsr.sar */, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", 88 /* xt_iclass_xsr.sar */, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", 92 /* xt_iclass_rsr.176 */, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "rsr.208", 93 /* xt_iclass_rsr.208 */, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", 94 /* xt_iclass_rsr.ps */, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", 95 /* xt_iclass_wsr.ps */, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", 96 /* xt_iclass_xsr.ps */, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", 133 /* xt_iclass_rsr.depc */, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", 134 /* xt_iclass_wsr.depc */, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", 135 /* xt_iclass_xsr.depc */, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", 145 /* xt_iclass_rsr.prid */, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rfi", 146 /* xt_iclass_rfi */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", 147 /* xt_iclass_wait */, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", 149 /* xt_iclass_wsr.intset */, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", 154 /* xt_iclass_break */, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", 155 /* xt_iclass_break.n */, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", 180 /* xt_iclass_rsr.icount */, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", 181 /* xt_iclass_wsr.icount */, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", 182 /* xt_iclass_xsr.icount */, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", 189 /* xt_iclass_rfdo */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", 190 /* xt_iclass_rfdd */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", 203 /* xt_iclass_icache */, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", 203 /* xt_iclass_icache */, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "iii", 204 /* xt_iclass_icache_inv */, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", 205 /* xt_iclass_licx */, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", 205 /* xt_iclass_licx */, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", 206 /* xt_iclass_sicx */, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", 206 /* xt_iclass_sicx */, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", 207 /* xt_iclass_dcache */, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", 207 /* xt_iclass_dcache */, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", 208 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", 208 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", 209 /* xt_iclass_dcache_inv */, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", 209 /* xt_iclass_dcache_inv */, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "sdct", 211 /* xt_iclass_sdct */, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", 212 /* xt_iclass_ldct */, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", 225 /* xt_iclass_idtlb */, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", 227 /* xt_iclass_wdtlb */, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", 228 /* xt_iclass_iitlb */, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", 229 /* xt_iclass_ritlb */, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", 229 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", 229 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", 230 /* xt_iclass_witlb */, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", 231 /* xt_iclass_ldpte */, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", 232 /* xt_iclass_hwwitlba */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "nsa", 234 /* xt_iclass_nsa */, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", 234 /* xt_iclass_nsa */, + 0, + Opcode_nsau_encode_fns, 0, 0 } +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 77; /* ill */ + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 96; /* ret */ + case 1: + return 14; /* retw */ + case 2: + return 79; /* jx */ + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 75; /* callx0 */ + case 1: + return 10; /* callx4 */ + case 2: + return 9; /* callx8 */ + case 3: + return 8; /* callx12 */ + } + break; + } + break; + case 1: + return 12; /* movsp */ + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 114; /* isync */ + case 1: + return 115; /* rsync */ + case 2: + return 116; /* esync */ + case 3: + return 117; /* dsync */ + case 8: + return 0; /* excw */ + case 12: + return 112; /* memw */ + case 13: + return 113; /* extw */ + case 15: + return 95; /* nop */ + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 1; /* rfe */ + case 2: + return 2; /* rfde */ + case 4: + return 16; /* rfwo */ + case 5: + return 17; /* rfwu */ + } + break; + case 1: + return 188; /* rfi */ + } + break; + case 4: + return 196; /* break */ + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 3; /* syscall */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 4; /* simcall */ + break; + } + break; + case 6: + return 118; /* rsil */ + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return 189; /* waiti */ + break; + } + break; + case 1: + return 47; /* and */ + case 2: + return 48; /* or */ + case 3: + return 49; /* xor */ + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 100; /* ssr */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 101; /* ssl */ + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return 102; /* ssa8l */ + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return 103; /* ssa8b */ + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return 104; /* ssai */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return 13; /* rotw */ + break; + case 14: + return 289; /* nsa */ + case 15: + return 290; /* nsau */ + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return 287; /* hwwitlba */ + case 3: + return 283; /* ritlb0 */ + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return 281; /* iitlb */ + break; + case 5: + return 282; /* pitlb */ + case 6: + return 285; /* witlb */ + case 7: + return 284; /* ritlb1 */ + case 9: + return 288; /* hwwdtlba */ + case 11: + return 278; /* rdtlb0 */ + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return 276; /* idtlb */ + break; + case 13: + return 277; /* pdtlb */ + case 14: + return 280; /* wdtlb */ + case 15: + return 279; /* rdtlb1 */ + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 93; /* neg */ + case 1: + return 94; /* abs */ + } + break; + case 8: + return 39; /* add */ + case 9: + return 41; /* addx2 */ + case 10: + return 42; /* addx4 */ + case 11: + return 43; /* addx8 */ + case 12: + return 40; /* sub */ + case 13: + return 44; /* subx2 */ + case 14: + return 45; /* subx4 */ + case 15: + return 46; /* subx8 */ + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return 109; /* slli */ + case 2: + case 3: + return 110; /* srai */ + case 4: + return 111; /* srli */ + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 127; /* xsr.lbeg */ + case 1: + return 121; /* xsr.lend */ + case 2: + return 124; /* xsr.lcount */ + case 3: + return 130; /* xsr.sar */ + case 5: + return 133; /* xsr.litbase */ + case 72: + return 22; /* xsr.windowbase */ + case 73: + return 25; /* xsr.windowstart */ + case 83: + return 266; /* xsr.ptevaddr */ + case 90: + return 269; /* xsr.rasid */ + case 91: + return 272; /* xsr.itlbcfg */ + case 92: + return 275; /* xsr.dtlbcfg */ + case 96: + return 218; /* xsr.ibreakenable */ + case 104: + return 230; /* xsr.ddr */ + case 128: + return 212; /* xsr.ibreaka0 */ + case 129: + return 215; /* xsr.ibreaka1 */ + case 144: + return 200; /* xsr.dbreaka0 */ + case 145: + return 206; /* xsr.dbreaka1 */ + case 160: + return 203; /* xsr.dbreakc0 */ + case 161: + return 209; /* xsr.dbreakc1 */ + case 177: + return 141; /* xsr.epc1 */ + case 178: + return 147; /* xsr.epc2 */ + case 179: + return 153; /* xsr.epc3 */ + case 180: + return 159; /* xsr.epc4 */ + case 192: + return 177; /* xsr.depc */ + case 194: + return 165; /* xsr.eps2 */ + case 195: + return 168; /* xsr.eps3 */ + case 196: + return 171; /* xsr.eps4 */ + case 209: + return 144; /* xsr.excsave1 */ + case 210: + return 150; /* xsr.excsave2 */ + case 211: + return 156; /* xsr.excsave3 */ + case 212: + return 162; /* xsr.excsave4 */ + case 228: + return 195; /* xsr.intenable */ + case 230: + return 138; /* xsr.ps */ + case 232: + return 180; /* xsr.exccause */ + case 233: + return 221; /* xsr.debugcause */ + case 234: + return 235; /* xsr.ccount */ + case 236: + return 224; /* xsr.icount */ + case 237: + return 227; /* xsr.icountlevel */ + case 238: + return 174; /* xsr.excvaddr */ + case 240: + return 238; /* xsr.ccompare0 */ + case 241: + return 241; /* xsr.ccompare1 */ + case 242: + return 244; /* xsr.ccompare2 */ + case 244: + return 183; /* xsr.misc0 */ + case 245: + return 186; /* xsr.misc1 */ + } + break; + case 8: + return 106; /* src */ + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return 107; /* srl */ + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return 105; /* sll */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return 108; /* sra */ + break; + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 248; /* lict */ + case 1: + return 250; /* sict */ + case 2: + return 249; /* licw */ + case 3: + return 251; /* sicw */ + case 8: + return 263; /* ldct */ + case 9: + return 262; /* sdct */ + case 14: + if (Field_t_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0) + return 231; /* rfdo */ + if (Field_t_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0) + return 232; /* rfdd */ + break; + case 15: + return 286; /* ldpte */ + } + break; + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 125; /* rsr.lbeg */ + case 1: + return 119; /* rsr.lend */ + case 2: + return 122; /* rsr.lcount */ + case 3: + return 128; /* rsr.sar */ + case 5: + return 131; /* rsr.litbase */ + case 72: + return 20; /* rsr.windowbase */ + case 73: + return 23; /* rsr.windowstart */ + case 83: + return 265; /* rsr.ptevaddr */ + case 90: + return 267; /* rsr.rasid */ + case 91: + return 270; /* rsr.itlbcfg */ + case 92: + return 273; /* rsr.dtlbcfg */ + case 96: + return 216; /* rsr.ibreakenable */ + case 104: + return 228; /* rsr.ddr */ + case 128: + return 210; /* rsr.ibreaka0 */ + case 129: + return 213; /* rsr.ibreaka1 */ + case 144: + return 198; /* rsr.dbreaka0 */ + case 145: + return 204; /* rsr.dbreaka1 */ + case 160: + return 201; /* rsr.dbreakc0 */ + case 161: + return 207; /* rsr.dbreakc1 */ + case 176: + return 134; /* rsr.176 */ + case 177: + return 139; /* rsr.epc1 */ + case 178: + return 145; /* rsr.epc2 */ + case 179: + return 151; /* rsr.epc3 */ + case 180: + return 157; /* rsr.epc4 */ + case 192: + return 175; /* rsr.depc */ + case 194: + return 163; /* rsr.eps2 */ + case 195: + return 166; /* rsr.eps3 */ + case 196: + return 169; /* rsr.eps4 */ + case 208: + return 135; /* rsr.208 */ + case 209: + return 142; /* rsr.excsave1 */ + case 210: + return 148; /* rsr.excsave2 */ + case 211: + return 154; /* rsr.excsave3 */ + case 212: + return 160; /* rsr.excsave4 */ + case 226: + return 190; /* rsr.interrupt */ + case 228: + return 193; /* rsr.intenable */ + case 230: + return 136; /* rsr.ps */ + case 232: + return 178; /* rsr.exccause */ + case 233: + return 219; /* rsr.debugcause */ + case 234: + return 233; /* rsr.ccount */ + case 235: + return 187; /* rsr.prid */ + case 236: + return 222; /* rsr.icount */ + case 237: + return 225; /* rsr.icountlevel */ + case 238: + return 172; /* rsr.excvaddr */ + case 240: + return 236; /* rsr.ccompare0 */ + case 241: + return 239; /* rsr.ccompare1 */ + case 242: + return 242; /* rsr.ccompare2 */ + case 244: + return 181; /* rsr.misc0 */ + case 245: + return 184; /* rsr.misc1 */ + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 126; /* wsr.lbeg */ + case 1: + return 120; /* wsr.lend */ + case 2: + return 123; /* wsr.lcount */ + case 3: + return 129; /* wsr.sar */ + case 5: + return 132; /* wsr.litbase */ + case 72: + return 21; /* wsr.windowbase */ + case 73: + return 24; /* wsr.windowstart */ + case 83: + return 264; /* wsr.ptevaddr */ + case 90: + return 268; /* wsr.rasid */ + case 91: + return 271; /* wsr.itlbcfg */ + case 92: + return 274; /* wsr.dtlbcfg */ + case 96: + return 217; /* wsr.ibreakenable */ + case 104: + return 229; /* wsr.ddr */ + case 128: + return 211; /* wsr.ibreaka0 */ + case 129: + return 214; /* wsr.ibreaka1 */ + case 144: + return 199; /* wsr.dbreaka0 */ + case 145: + return 205; /* wsr.dbreaka1 */ + case 160: + return 202; /* wsr.dbreakc0 */ + case 161: + return 208; /* wsr.dbreakc1 */ + case 177: + return 140; /* wsr.epc1 */ + case 178: + return 146; /* wsr.epc2 */ + case 179: + return 152; /* wsr.epc3 */ + case 180: + return 158; /* wsr.epc4 */ + case 192: + return 176; /* wsr.depc */ + case 194: + return 164; /* wsr.eps2 */ + case 195: + return 167; /* wsr.eps3 */ + case 196: + return 170; /* wsr.eps4 */ + case 209: + return 143; /* wsr.excsave1 */ + case 210: + return 149; /* wsr.excsave2 */ + case 211: + return 155; /* wsr.excsave3 */ + case 212: + return 161; /* wsr.excsave4 */ + case 226: + return 191; /* wsr.intset */ + case 227: + return 192; /* wsr.intclear */ + case 228: + return 194; /* wsr.intenable */ + case 230: + return 137; /* wsr.ps */ + case 232: + return 179; /* wsr.exccause */ + case 233: + return 220; /* wsr.debugcause */ + case 234: + return 234; /* wsr.ccount */ + case 236: + return 223; /* wsr.icount */ + case 237: + return 226; /* wsr.icountlevel */ + case 238: + return 173; /* wsr.excvaddr */ + case 240: + return 237; /* wsr.ccompare0 */ + case 241: + return 240; /* wsr.ccompare1 */ + case 242: + return 243; /* wsr.ccompare2 */ + case 244: + return 182; /* wsr.misc0 */ + case 245: + return 185; /* wsr.misc1 */ + } + break; + case 8: + return 89; /* moveqz */ + case 9: + return 90; /* movnez */ + case 10: + return 91; /* movltz */ + case 11: + return 92; /* movgez */ + } + break; + case 4: + case 5: + return 76; /* extui */ + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return 18; /* l32e */ + case 4: + return 19; /* s32e */ + } + break; + } + break; + case 1: + return 83; /* l32r */ + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 84; /* l8ui */ + case 1: + return 80; /* l16ui */ + case 2: + return 82; /* l32i */ + case 4: + return 99; /* s8i */ + case 5: + return 97; /* s16i */ + case 6: + return 98; /* s32i */ + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 258; /* dpfr */ + case 1: + return 259; /* dpfw */ + case 2: + return 260; /* dpfro */ + case 3: + return 261; /* dpfwo */ + case 4: + return 252; /* dhwb */ + case 5: + return 253; /* dhwbi */ + case 6: + return 256; /* dhi */ + case 7: + return 257; /* dii */ + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + return 254; /* diwb */ + case 5: + return 255; /* diwbi */ + } + break; + case 12: + return 245; /* ipf */ + case 14: + return 246; /* ihi */ + case 15: + return 247; /* iii */ + } + break; + case 9: + return 81; /* l16si */ + case 10: + return 88; /* movi */ + case 12: + return 37; /* addi */ + case 13: + return 38; /* addmi */ + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 74; /* call0 */ + case 1: + return 7; /* call4 */ + case 2: + return 6; /* call8 */ + case 3: + return 5; /* call12 */ + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 78; /* j */ + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 70; /* beqz */ + case 1: + return 71; /* bnez */ + case 2: + return 73; /* bltz */ + case 3: + return 72; /* bgez */ + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 50; /* beqi */ + case 1: + return 51; /* bnei */ + case 2: + return 53; /* blti */ + case 3: + return 52; /* bgei */ + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 11; /* entry */ + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return 85; /* loop */ + case 9: + return 86; /* loopnez */ + case 10: + return 87; /* loopgtz */ + } + break; + case 2: + return 57; /* bltui */ + case 3: + return 56; /* bgeui */ + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 65; /* bnone */ + case 1: + return 58; /* beq */ + case 2: + return 61; /* blt */ + case 3: + return 63; /* bltu */ + case 4: + return 66; /* ball */ + case 5: + return 68; /* bbc */ + case 6: + case 7: + return 54; /* bbci */ + case 8: + return 64; /* bany */ + case 9: + return 59; /* bne */ + case 10: + return 60; /* bge */ + case 11: + return 62; /* bgeu */ + case 12: + return 67; /* bnall */ + case 13: + return 69; /* bbs */ + case 14: + case 15: + return 55; /* bbsi */ + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return 33; /* movi.n */ + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return 28; /* beqz.n */ + case 1: + return 29; /* bnez.n */ + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return 32; /* mov.n */ + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return 35; /* ret.n */ + case 1: + return 15; /* retw.n */ + case 2: + return 197; /* break.n */ + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 34; /* nop.n */ + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return 31; /* l32i.n */ + case 9: + return 36; /* s32i.n */ + case 10: + return 26; /* add.n */ + case 11: + return 27; /* addi.n */ + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x800000; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc00000; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x800000) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc00000) == 0x800000) + return 1; /* x16a */ + if ((insn[0] & 0xe00000) == 0xc00000) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = (insn[0] >> 4) & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 1 /* big-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 39 /* num_fields */, + 70, operands, + 235, iclasses, + 291, opcodes, 0, + 1, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 0, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 9196178..1c982a0 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -93,6 +93,14 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) return oc; } +static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + + info->private_data = cpu->env.config->isa; + info->print_insn = print_insn_xtensa; +} + static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -164,6 +172,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->do_unassigned_access = xtensa_cpu_do_unassigned_access; #endif cc->debug_excp_handler = xtensa_breakpoint_handler; + cc->disas_set_info = xtensa_cpu_disas_set_info; cc->tcg_initialize = xtensa_translate_init; dc->vmsd = &vmstate_xtensa_cpu; } diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b17d7d9..d9404aa 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -37,6 +37,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#include "xtensa-isa.h" #define NB_MMU_MODES 4 @@ -107,6 +108,7 @@ enum { }; enum { + EXPSTATE = 230, THREADPTR = 231, FCR = 232, FSR = 233, @@ -126,6 +128,7 @@ enum { WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, + MMID = 89, RASID = 90, ITLBCFG = 91, DTLBCFG = 92, @@ -133,6 +136,7 @@ enum { MEMCTL = 97, CACHEATTR = 98, ATOMCTL = 99, + DDR = 104, IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, @@ -205,6 +209,8 @@ enum { #define MEMCTL_DSNP 0x2 #define MEMCTL_IL0EN 0x1 +#define MAX_INSN_LENGTH 64 +#define MAX_OPCODE_ARGS 16 #define MAX_NAREG 64 #define MAX_NINTERRUPT 32 #define MAX_NLEVEL 6 @@ -330,6 +336,24 @@ typedef struct XtensaMemory { } location[MAX_NMEMORY]; } XtensaMemory; +typedef struct DisasContext DisasContext; +typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]); + +typedef struct XtensaOpcodeOps { + const char *name; + XtensaOpcodeOp translate; + const uint32_t *par; +} XtensaOpcodeOps; + +typedef struct XtensaOpcodeTranslators { + unsigned num_opcodes; + const XtensaOpcodeOps *opcode; +} XtensaOpcodeTranslators; + +extern const XtensaOpcodeTranslators xtensa_core_opcodes; +extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; + struct XtensaConfig { const char *name; uint64_t options; @@ -370,6 +394,11 @@ struct XtensaConfig { uint32_t configid[2]; + void *isa_internal; + xtensa_isa isa; + XtensaOpcodeOps **opcode_ops; + const XtensaOpcodeTranslators **opcode_translators; + uint32_t clock_freq_khz; xtensa_tlb itlb; @@ -522,6 +551,8 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, env->static_vectors = n; } void xtensa_runstall(CPUXtensaState *env, bool runstall); +XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, + const char *opcode); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 216f198..5009fec 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -52,10 +52,47 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs = config->gdb_regmap.num_regs; } +static void init_libisa(XtensaConfig *config) +{ + unsigned i, j; + unsigned opcodes; + + config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); + assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); + opcodes = xtensa_isa_num_opcodes(config->isa); + config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); + + for (i = 0; i < opcodes; ++i) { + const char *opc_name = xtensa_opcode_name(config->isa, i); + XtensaOpcodeOps *ops = NULL; + + assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS); + if (!config->opcode_translators) { + ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name); + } else { + for (j = 0; !ops && config->opcode_translators[j]; ++j) { + ops = xtensa_find_opcode_ops(config->opcode_translators[j], + opc_name); + } + } +#ifdef DEBUG + if (ops == NULL) { + fprintf(stderr, + "opcode translator not found for %s's opcode '%s'\n", + config->name, opc_name); + } +#endif + config->opcode_ops[i] = ops; + } +} + void xtensa_finalize_config(XtensaConfig *config) { unsigned i, n = 0; + if (config->isa_internal) { + init_libisa(config); + } if (config->gdb_regmap.num_regs) { return; } diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index cebb6e9..32255ee 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -23,6 +23,17 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \ --xform='s/core/core-isa/' config/core.h tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c +# +# Fix up known issues in the xtensa-modules.c +# +tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \ + sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \ + -e '/^int num_bypass_groups()/,/}/d' \ + -e '/^int num_bypass_group_chunks()/,/}/d' \ + -e '/^uint32 \*bypass_entry(int i)/,/}/d' \ + -e '/^#include "ansidecl.h"/d' \ + -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \ + > "$TARGET"/xtensa-modules.c cat <<EOF > "${TARGET}.c" #include "qemu/osdep.h" @@ -35,6 +46,9 @@ cat <<EOF > "${TARGET}.c" #include "core-$NAME/core-isa.h" #include "overlay_tool.h" +#define xtensa_modules xtensa_modules_$NAME +#include "core-$NAME/xtensa-modules.c" + static XtensaConfig $NAME __attribute__((unused)) = { .name = "$NAME", .gdb_regmap = { @@ -42,6 +56,7 @@ static XtensaConfig $NAME __attribute__((unused)) = { #include "core-$NAME/gdb-config.c" } }, + .isa_internal = &xtensa_modules, .clock_freq_khz = $FREQ, DEFAULT_SECTIONS }; diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 3d990c0..0125528 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -249,7 +249,7 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) if (windowstart & ((1 << callinc) - 1)) { HELPER(window_check)(env, pc, callinc); } - env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3); + env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm; rotate_window(env, callinc); env->sregs[WINDOW_START] |= windowstart_bit(env->sregs[WINDOW_BASE], env); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 20f7ddf..4bdfcd2 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -59,7 +59,6 @@ typedef struct DisasContext { int ring; uint32_t lbeg; uint32_t lend; - TCGv_i32 litbase; int is_jmp; int singlestep_enabled; @@ -75,6 +74,10 @@ typedef struct DisasContext { TCGv_i32 next_icount; unsigned cpenable; + + uint32_t *raw_arg; + xtensa_insnbuf insnbuf; + xtensa_insnbuf slotbuf; } DisasContext; static TCGv_i32 cpu_pc; @@ -132,6 +135,7 @@ static const XtensaReg sregnames[256] = { [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), + [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), @@ -139,6 +143,7 @@ static const XtensaReg sregnames[256] = { [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), + [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), @@ -199,6 +204,7 @@ static const XtensaReg sregnames[256] = { }; static const XtensaReg uregnames[256] = { + [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), @@ -252,31 +258,11 @@ void xtensa_translate_init(void) } } -static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) -{ - return xtensa_option_bits_enabled(dc->config, opt); -} - static inline bool option_enabled(DisasContext *dc, int opt) { return xtensa_option_enabled(dc->config, opt); } -static void init_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - dc->litbase = tcg_temp_local_new_i32(); - tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); - } -} - -static void reset_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_temp_free(dc->litbase); - } -} - static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit = false; @@ -469,21 +455,21 @@ static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) } static void gen_brcond(DisasContext *dc, TCGCond cond, - TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) + TCGv_i32 t0, TCGv_i32 t1, uint32_t addr) { TCGLabel *label = gen_new_label(); tcg_gen_brcond_i32(cond, t0, t1, label); gen_jumpi_check_loop_end(dc, 0); gen_set_label(label); - gen_jumpi(dc, dc->pc + offset, 1); + gen_jumpi(dc, addr, 1); } static void gen_brcondi(DisasContext *dc, TCGCond cond, - TCGv_i32 t0, uint32_t t1, uint32_t offset) + TCGv_i32 t0, uint32_t t1, uint32_t addr) { TCGv_i32 tmp = tcg_const_i32(t1); - gen_brcond(dc, cond, t0, tmp, offset); + gen_brcond(dc, cond, t0, tmp, addr); tcg_temp_free(tmp); } @@ -945,2164 +931,98 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static inline unsigned xtensa_op0_insn_len(unsigned op0) +static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) { - return op0 >= 8 ? 2 : 3; + return xtensa_isa_length_from_chars(dc->config->isa, &op0); } static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { -#define HAS_OPTION_BITS(opt) do { \ - if (!option_bits_enabled(dc, opt)) { \ - qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \ - __FILE__, __LINE__); \ - goto invalid_opcode; \ - } \ - } while (0) - -#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) - -#define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) -#define RESERVED() do { \ - qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ - dc->pc, b0, b1, b2, __FILE__, __LINE__); \ - goto invalid_opcode; \ - } while (0) - - -#ifdef TARGET_WORDS_BIGENDIAN -#define OP0 (((b0) & 0xf0) >> 4) -#define OP1 (((b2) & 0xf0) >> 4) -#define OP2 ((b2) & 0xf) -#define RRR_R ((b1) & 0xf) -#define RRR_S (((b1) & 0xf0) >> 4) -#define RRR_T ((b0) & 0xf) -#else -#define OP0 (((b0) & 0xf)) -#define OP1 (((b2) & 0xf)) -#define OP2 (((b2) & 0xf0) >> 4) -#define RRR_R (((b1) & 0xf0) >> 4) -#define RRR_S (((b1) & 0xf)) -#define RRR_T (((b0) & 0xf0) >> 4) -#endif -#define RRR_X ((RRR_R & 0x4) >> 2) -#define RRR_Y ((RRR_T & 0x4) >> 2) -#define RRR_W (RRR_R & 0x3) - -#define RRRN_R RRR_R -#define RRRN_S RRR_S -#define RRRN_T RRR_T - -#define RRI4_R RRR_R -#define RRI4_S RRR_S -#define RRI4_T RRR_T -#ifdef TARGET_WORDS_BIGENDIAN -#define RRI4_IMM4 ((b2) & 0xf) -#else -#define RRI4_IMM4 (((b2) & 0xf0) >> 4) -#endif - -#define RRI8_R RRR_R -#define RRI8_S RRR_S -#define RRI8_T RRR_T -#define RRI8_IMM8 (b2) -#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) - -#ifdef TARGET_WORDS_BIGENDIAN -#define RI16_IMM16 (((b1) << 8) | (b2)) -#else -#define RI16_IMM16 (((b2) << 8) | (b1)) -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define CALL_N (((b0) & 0xc) >> 2) -#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) -#else -#define CALL_N (((b0) & 0x30) >> 4) -#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) -#endif -#define CALL_OFFSET_SE \ - (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) - -#define CALLX_N CALL_N -#ifdef TARGET_WORDS_BIGENDIAN -#define CALLX_M ((b0) & 0x3) -#else -#define CALLX_M (((b0) & 0xc0) >> 6) -#endif -#define CALLX_S RRR_S - -#define BRI12_M CALLX_M -#define BRI12_S RRR_S -#ifdef TARGET_WORDS_BIGENDIAN -#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) -#else -#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) -#endif -#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) - -#define BRI8_M BRI12_M -#define BRI8_R RRI8_R -#define BRI8_S RRI8_S -#define BRI8_IMM8 RRI8_IMM8 -#define BRI8_IMM8_SE RRI8_IMM8_SE - -#define RSR_SR (b1) - - uint8_t b0 = cpu_ldub_code(env, dc->pc); - uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); - uint8_t b2 = 0; - unsigned len = xtensa_op0_insn_len(OP0); - - static const uint32_t B4CONST[] = { - 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 - }; - - static const uint32_t B4CONSTU[] = { - 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 - }; - - switch (len) { - case 2: - HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); - break; - - case 3: - b2 = cpu_ldub_code(env, dc->pc + 2); - break; + xtensa_isa isa = dc->config->isa; + unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)}; + unsigned len = xtensa_op0_insn_len(dc, b[0]); + xtensa_format fmt; + unsigned slot, slots; + unsigned i; - default: - RESERVED(); + if (len == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unknown instruction length (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - dc->next_pc = dc->pc + len; - - switch (OP0) { - case 0: /*QRST*/ - switch (OP1) { - case 0: /*RST0*/ - switch (OP2) { - case 0: /*ST0*/ - if ((RRR_R & 0xc) == 0x8) { - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - } - - switch (RRR_R) { - case 0: /*SNM0*/ - switch (CALLX_M) { - case 0: /*ILL*/ - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - break; - - case 1: /*reserved*/ - RESERVED(); - break; - - case 2: /*JR*/ - switch (CALLX_N) { - case 0: /*RET*/ - case 2: /*JX*/ - if (gen_window_check1(dc, CALLX_S)) { - gen_jump(dc, cpu_R[CALLX_S]); - } - break; - - case 1: /*RETWw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 3: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*CALLX*/ - if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) { - break; - } - switch (CALLX_N) { - case 0: /*CALLX0*/ - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 1: /*CALLX4w*/ - case 2: /*CALLX8w*/ - case 3: /*CALLX12w*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); - gen_callw(dc, CALLX_N, tmp); - tcg_temp_free(tmp); - } - break; - } - break; - } - break; - - case 1: /*MOVSPw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_window_check2(dc, RRR_T, RRR_S)) { - TCGv_i32 pc = tcg_const_i32(dc->pc); - gen_helper_movsp(cpu_env, pc); - tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); - tcg_temp_free(pc); - } - break; - - case 2: /*SYNC*/ - switch (RRR_T) { - case 0: /*ISYNC*/ - break; - - case 1: /*RSYNC*/ - break; - - case 2: /*ESYNC*/ - break; - - case 3: /*DSYNC*/ - break; - - case 8: /*EXCW*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - break; - - case 12: /*MEMW*/ - break; - - case 13: /*EXTW*/ - break; - - case 15: /*NOP*/ - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*RFEIx*/ - switch (RRR_T) { - case 0: /*RFETx*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - switch (RRR_S) { - case 0: /*RFEx*/ - if (gen_check_privilege(dc)) { - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); - } - break; - - case 1: /*RFUEx*/ - RESERVED(); - break; - - case 2: /*RFDEx*/ - if (gen_check_privilege(dc)) { - gen_jump(dc, cpu_SR[ - dc->config->ndepc ? DEPC : EPC1]); - } - break; - - case 4: /*RFWOw*/ - case 5: /*RFWUw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { - TCGv_i32 tmp = tcg_const_i32(1); - - tcg_gen_andi_i32( - cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); - - if (RRR_S == 4) { - tcg_gen_andc_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } else { - tcg_gen_or_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } - - gen_helper_restore_owb(cpu_env); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); - - tcg_temp_free(tmp); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 1: /*RFIx*/ - HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); - if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { - if (gen_check_privilege(dc)) { - tcg_gen_mov_i32(cpu_SR[PS], - cpu_SR[EPS2 + RRR_S - 2]); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - } - break; - - case 2: /*RFME*/ - TBD(); - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 4: /*BREAKx*/ - HAS_OPTION(XTENSA_OPTION_DEBUG); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_BI); - } - break; - - case 5: /*SYSCALLx*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - switch (RRR_S) { - case 0: /*SYSCALLx*/ - gen_exception_cause(dc, SYSCALL_CAUSE); - break; - - case 1: /*SIMCALL*/ - if (semihosting_enabled()) { - if (gen_check_privilege(dc)) { - gen_helper_simcall(cpu_env); - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - } - break; - - default: - RESERVED(); - break; - } - break; - - case 6: /*RSILx*/ - HAS_OPTION(XTENSA_OPTION_INTERRUPT); - if (gen_check_privilege(dc) && - gen_window_check1(dc, RRR_T)) { - tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); - tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); - gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); - } - break; - - case 7: /*WAITIx*/ - HAS_OPTION(XTENSA_OPTION_INTERRUPT); - if (gen_check_privilege(dc)) { - gen_waiti(dc, RRR_S); - } - break; - - case 8: /*ANY4p*/ - case 9: /*ALL4p*/ - case 10: /*ANY8p*/ - case 11: /*ALL8p*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - { - const unsigned shift = (RRR_R & 2) ? 8 : 4; - TCGv_i32 mask = tcg_const_i32( - ((1 << shift) - 1) << RRR_S); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_and_i32(tmp, cpu_SR[BR], mask); - if (RRR_R & 1) { /*ALL*/ - tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); - } else { /*ANY*/ - tcg_gen_add_i32(tmp, tmp, mask); - } - tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], - tmp, RRR_T, 1); - tcg_temp_free(mask); - tcg_temp_free(tmp); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 1: /*AND*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 2: /*OR*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 3: /*XOR*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 4: /*ST1*/ - switch (RRR_R) { - case 0: /*SSR*/ - if (gen_window_check1(dc, RRR_S)) { - gen_right_shift_sar(dc, cpu_R[RRR_S]); - } - break; - - case 1: /*SSL*/ - if (gen_window_check1(dc, RRR_S)) { - gen_left_shift_sar(dc, cpu_R[RRR_S]); - } - break; - - case 2: /*SSA8L*/ - if (gen_window_check1(dc, RRR_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); - gen_right_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 3: /*SSA8B*/ - if (gen_window_check1(dc, RRR_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); - gen_left_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 4: /*SSAI*/ - { - TCGv_i32 tmp = tcg_const_i32( - RRR_S | ((RRR_T & 1) << 4)); - gen_right_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 6: /*RER*/ - HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - gen_helper_rer(cpu_R[RRR_T], cpu_env, cpu_R[RRR_S]); - } - break; - - case 7: /*WER*/ - HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - gen_helper_wer(cpu_env, cpu_R[RRR_T], cpu_R[RRR_S]); - } - break; - - case 8: /*ROTWw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { - TCGv_i32 tmp = tcg_const_i32( - RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); - gen_helper_rotw(cpu_env, tmp); - tcg_temp_free(tmp); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - } - break; - - case 14: /*NSAu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); - if (gen_window_check2(dc, RRR_S, RRR_T)) { - tcg_gen_clrsb_i32(cpu_R[RRR_T], cpu_R[RRR_S]); - } - break; - - case 15: /*NSAUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); - if (gen_window_check2(dc, RRR_S, RRR_T)) { - tcg_gen_clzi_i32(cpu_R[RRR_T], cpu_R[RRR_S], 32); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 5: /*TLB*/ - HAS_OPTION_BITS( - XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); - - switch (RRR_R & 7) { - case 3: /*RITLB0*/ /*RDTLB0*/ - gen_helper_rtlb0(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - case 4: /*IITLB*/ /*IDTLB*/ - gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - break; - - case 5: /*PITLB*/ /*PDTLB*/ - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_ptlb(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - case 6: /*WITLB*/ /*WDTLB*/ - gen_helper_wtlb( - cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - break; - - case 7: /*RITLB1*/ /*RDTLB1*/ - gen_helper_rtlb1(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - default: - tcg_temp_free(dtlb); - RESERVED(); - break; - } - tcg_temp_free(dtlb); - } - break; - - case 6: /*RT0*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - switch (RRR_S) { - case 0: /*NEG*/ - tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); - break; - - case 1: /*ABS*/ - { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 neg = tcg_temp_new_i32(); - - tcg_gen_neg_i32(neg, cpu_R[RRR_T]); - tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], - cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); - tcg_temp_free(neg); - tcg_temp_free(zero); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 7: /*reserved*/ - RESERVED(); - break; - - case 8: /*ADD*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 9: /*ADD**/ - case 10: - case 11: - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); - tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); - tcg_temp_free(tmp); - } - break; - - case 12: /*SUB*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 13: /*SUB**/ - case 14: - case 15: - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); - tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); - tcg_temp_free(tmp); - } - break; - } - break; - - case 1: /*RST1*/ - switch (OP2) { - case 0: /*SLLI*/ - case 1: - if (gen_window_check2(dc, RRR_R, RRR_S)) { - tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], - 32 - (RRR_T | ((OP2 & 1) << 4))); - } - break; - - case 2: /*SRAI*/ - case 3: - if (gen_window_check2(dc, RRR_R, RRR_T)) { - tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], - RRR_S | ((OP2 & 1) << 4)); - } - break; - - case 4: /*SRLI*/ - if (gen_window_check2(dc, RRR_R, RRR_T)) { - tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); - } - break; - - case 6: /*XSR*/ - if (gen_check_sr(dc, RSR_SR, SR_X) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - bool rsr_end, wsr_end; - - tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); - rsr_end = gen_rsr(dc, cpu_R[RRR_T], RSR_SR); - wsr_end = gen_wsr(dc, RSR_SR, tmp); - tcg_temp_free(tmp); - if (rsr_end && !wsr_end) { - gen_jumpi_check_loop_end(dc, 0); - } - } - break; - - /* - * Note: 64 bit ops are used here solely because SAR values - * have range 0..63 - */ -#define gen_shift_reg(cmd, reg) do { \ - TCGv_i64 tmp = tcg_temp_new_i64(); \ - tcg_gen_extu_i32_i64(tmp, reg); \ - tcg_gen_##cmd##_i64(v, v, tmp); \ - tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \ - tcg_temp_free_i64(v); \ - tcg_temp_free_i64(tmp); \ - } while (0) - -#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) - - case 8: /*SRC*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); - gen_shift(shr); - } - break; - - case 9: /*SRL*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - if (dc->sar_5bit) { - tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); - gen_shift(shr); - } - break; - - case 10: /*SLL*/ - if (!gen_window_check2(dc, RRR_R, RRR_S)) { - break; - } - if (dc->sar_m32_5bit) { - tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - TCGv_i32 s = tcg_const_i32(32); - tcg_gen_sub_i32(s, s, cpu_SR[SAR]); - tcg_gen_andi_i32(s, s, 0x3f); - tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); - gen_shift_reg(shl, s); - tcg_temp_free(s); - } - break; - - case 11: /*SRA*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - if (dc->sar_5bit) { - tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); - gen_shift(sar); - } - break; -#undef gen_shift -#undef gen_shift_reg - - case 12: /*MUL16U*/ - HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 v1 = tcg_temp_new_i32(); - TCGv_i32 v2 = tcg_temp_new_i32(); - tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); - tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); - tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); - tcg_temp_free(v2); - tcg_temp_free(v1); - } - break; - - case 13: /*MUL16S*/ - HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 v1 = tcg_temp_new_i32(); - TCGv_i32 v2 = tcg_temp_new_i32(); - tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); - tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); - tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); - tcg_temp_free(v2); - tcg_temp_free(v1); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 2: /*RST2*/ - if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - break; - } - - if (OP2 >= 12) { - HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); - TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); - gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); - gen_set_label(label); - } - - switch (OP2) { -#define BOOLEAN_LOGIC(fn, r, s, t) \ - do { \ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ - TCGv_i32 tmp1 = tcg_temp_new_i32(); \ - TCGv_i32 tmp2 = tcg_temp_new_i32(); \ - \ - tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ - tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ - tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ - tcg_temp_free(tmp1); \ - tcg_temp_free(tmp2); \ - } while (0) - - case 0: /*ANDBp*/ - BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); - break; - - case 1: /*ANDBCp*/ - BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); - break; - - case 2: /*ORBp*/ - BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); - break; - - case 3: /*ORBCp*/ - BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); - break; - - case 4: /*XORBp*/ - BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); - break; - -#undef BOOLEAN_LOGIC - - case 8: /*MULLi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); - tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - case 10: /*MULUHi*/ - case 11: /*MULSHi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); - { - TCGv lo = tcg_temp_new(); - - if (OP2 == 10) { - tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } else { - tcg_gen_muls2_i32(lo, cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - tcg_temp_free(lo); - } - break; - - case 12: /*QUOUi*/ - tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - case 13: /*QUOSi*/ - case 15: /*REMSi*/ - { - TCGLabel *label1 = gen_new_label(); - TCGLabel *label2 = gen_new_label(); - - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, - label1); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, - label1); - tcg_gen_movi_i32(cpu_R[RRR_R], - OP2 == 13 ? 0x80000000 : 0); - tcg_gen_br(label2); - gen_set_label(label1); - if (OP2 == 13) { - tcg_gen_div_i32(cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } else { - tcg_gen_rem_i32(cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - gen_set_label(label2); - } - break; - - case 14: /*REMUi*/ - tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*RST3*/ - switch (OP2) { - case 0: /*RSR*/ - if (gen_check_sr(dc, RSR_SR, SR_R) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - if (gen_rsr(dc, cpu_R[RRR_T], RSR_SR)) { - gen_jumpi_check_loop_end(dc, 0); - } - } - break; - - case 1: /*WSR*/ - if (gen_check_sr(dc, RSR_SR, SR_W) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); - } - break; - - case 2: /*SEXTu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - int shift = 24 - RRR_T; - - if (shift == 24) { - tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); - } else if (shift == 16) { - tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); - } else { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); - tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); - tcg_temp_free(tmp); - } - } - break; - - case 3: /*CLAMPSu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - TCGv_i32 tmp1 = tcg_temp_new_i32(); - TCGv_i32 tmp2 = tcg_temp_new_i32(); - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); - tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); - tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); - - tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); - tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); - - tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, - cpu_R[RRR_S], tmp1); - tcg_temp_free(tmp1); - tcg_temp_free(tmp2); - tcg_temp_free(zero); - } - break; - - case 4: /*MINu*/ - case 5: /*MAXu*/ - case 6: /*MINUu*/ - case 7: /*MAXUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - static const TCGCond cond[] = { - TCG_COND_LE, - TCG_COND_GE, - TCG_COND_LEU, - TCG_COND_GEU - }; - tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 8: /*MOVEQZ*/ - case 9: /*MOVNEZ*/ - case 10: /*MOVLTZ*/ - case 11: /*MOVGEZ*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - static const TCGCond cond[] = { - TCG_COND_EQ, - TCG_COND_NE, - TCG_COND_LT, - TCG_COND_GE, - }; - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], - cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); - tcg_temp_free(zero); - } - break; - - case 12: /*MOVFp*/ - case 13: /*MOVTp*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); - tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, - cpu_R[RRR_R], tmp, zero, - cpu_R[RRR_S], cpu_R[RRR_R]); - - tcg_temp_free(tmp); - tcg_temp_free(zero); - } - break; - - case 14: /*RUR*/ - if (gen_window_check1(dc, RRR_R)) { - int st = (RRR_S << 4) + RRR_T; - if (uregnames[st].name) { - tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); - } else { - qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st); - TBD(); - } - } - break; - - case 15: /*WUR*/ - if (gen_window_check1(dc, RRR_T)) { - if (uregnames[RSR_SR].name) { - gen_wur(RSR_SR, cpu_R[RRR_T]); - } else { - qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR); - TBD(); - } - } - break; - - } - break; - - case 4: /*EXTUI*/ - case 5: - if (gen_window_check2(dc, RRR_R, RRR_T)) { - int shiftimm = RRR_S | ((OP1 & 1) << 4); - int maskimm = (1 << (OP2 + 1)) - 1; - - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); - tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); - tcg_temp_free(tmp); - } - break; - - case 6: /*CUST0*/ - RESERVED(); - break; - - case 7: /*CUST1*/ - RESERVED(); - break; - - case 8: /*LSCXp*/ - switch (OP2) { - case 0: /*LSXf*/ - case 1: /*LSXUf*/ - case 4: /*SSXf*/ - case 5: /*SSXUf*/ - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - if (gen_window_check2(dc, RRR_S, RRR_T) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); - gen_load_store_alignment(dc, 2, addr, false); - if (OP2 & 0x4) { - tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); - } - if (OP2 & 0x1) { - tcg_gen_mov_i32(cpu_R[RRR_S], addr); - } - tcg_temp_free(addr); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 9: /*LSC4*/ - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - switch (OP2) { - case 0: /*L32E*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRR_S], - (0xffffffc0 | (RRR_R << 2))); - tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); - tcg_temp_free(addr); - } - break; - - case 4: /*S32E*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRR_S], - (0xffffffc0 | (RRR_R << 2))); - tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); - tcg_temp_free(addr); - } - break; - - case 5: /*S32N*/ - if (gen_window_check2(dc, RRI4_S, RRI4_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - - tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); - gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); - tcg_temp_free(addr); - } - break; - - default: - RESERVED(); - break; - } - break; - - case 10: /*FP0*/ - /*DEPBITS*/ - if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], - OP2, RRR_R + 1); - break; - } - - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - switch (OP2) { - case 0: /*ADD.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_add_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 1: /*SUB.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 2: /*MUL.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 4: /*MADD.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_R], cpu_FR[RRR_S], - cpu_FR[RRR_T]); - } - break; - - case 5: /*MSUB.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_R], cpu_FR[RRR_S], - cpu_FR[RRR_T]); - } - break; - - case 8: /*ROUND.Sf*/ - case 9: /*TRUNC.Sf*/ - case 10: /*FLOOR.Sf*/ - case 11: /*CEIL.Sf*/ - case 14: /*UTRUNC.Sf*/ - if (gen_window_check1(dc, RRR_R) && - gen_check_cpenable(dc, 0)) { - static const unsigned rounding_mode_const[] = { - float_round_nearest_even, - float_round_to_zero, - float_round_down, - float_round_up, - [6] = float_round_to_zero, - }; - TCGv_i32 rounding_mode = tcg_const_i32( - rounding_mode_const[OP2 & 7]); - TCGv_i32 scale = tcg_const_i32(RRR_T); - - if (OP2 == 14) { - gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], - rounding_mode, scale); - } else { - gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], - rounding_mode, scale); - } - - tcg_temp_free(rounding_mode); - tcg_temp_free(scale); - } - break; - - case 12: /*FLOAT.Sf*/ - case 13: /*UFLOAT.Sf*/ - if (gen_window_check1(dc, RRR_S) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 scale = tcg_const_i32(-RRR_T); - - if (OP2 == 13) { - gen_helper_uitof(cpu_FR[RRR_R], cpu_env, - cpu_R[RRR_S], scale); - } else { - gen_helper_itof(cpu_FR[RRR_R], cpu_env, - cpu_R[RRR_S], scale); - } - tcg_temp_free(scale); - } - break; - - case 15: /*FP1OP*/ - switch (RRR_T) { - case 0: /*MOV.Sf*/ - if (gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 1: /*ABS.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 4: /*RFRf*/ - if (gen_window_check1(dc, RRR_R) && - gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 5: /*WFRf*/ - if (gen_window_check1(dc, RRR_S) && - gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); - } - break; - - case 6: /*NEG.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 11: /*FP1*/ - /*DEPBITS*/ - if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], - OP2 + 16, RRR_R + 1); - break; - } - - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - -#define gen_compare(rel, br, a, b) \ - do { \ - if (gen_check_cpenable(dc, 0)) { \ - TCGv_i32 bit = tcg_const_i32(1 << br); \ - \ - gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ - tcg_temp_free(bit); \ - } \ - } while (0) - - switch (OP2) { - case 1: /*UN.Sf*/ - gen_compare(un_s, RRR_R, RRR_S, RRR_T); - break; - - case 2: /*OEQ.Sf*/ - gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); - break; - - case 3: /*UEQ.Sf*/ - gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); - break; - - case 4: /*OLT.Sf*/ - gen_compare(olt_s, RRR_R, RRR_S, RRR_T); - break; - - case 5: /*ULT.Sf*/ - gen_compare(ult_s, RRR_R, RRR_S, RRR_T); - break; - - case 6: /*OLE.Sf*/ - gen_compare(ole_s, RRR_R, RRR_S, RRR_T); - break; - - case 7: /*ULE.Sf*/ - gen_compare(ule_s, RRR_R, RRR_S, RRR_T); - break; - -#undef gen_compare - - case 8: /*MOVEQZ.Sf*/ - case 9: /*MOVNEZ.Sf*/ - case 10: /*MOVLTZ.Sf*/ - case 11: /*MOVGEZ.Sf*/ - if (gen_window_check1(dc, RRR_T) && - gen_check_cpenable(dc, 0)) { - static const TCGCond cond[] = { - TCG_COND_EQ, - TCG_COND_NE, - TCG_COND_LT, - TCG_COND_GE, - }; - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], - cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); - tcg_temp_free(zero); - } - break; - - case 12: /*MOVF.Sf*/ - case 13: /*MOVT.Sf*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); - tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, - cpu_FR[RRR_R], tmp, zero, - cpu_FR[RRR_S], cpu_FR[RRR_R]); - - tcg_temp_free(tmp); - tcg_temp_free(zero); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 1: /*L32R*/ - if (gen_window_check1(dc, RRR_T)) { - TCGv_i32 tmp = tcg_const_i32( - ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? - 0 : ((dc->pc + 3) & ~3)) + - (0xfffc0000 | (RI16_IMM16 << 2))); - - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_gen_add_i32(tmp, tmp, dc->litbase); - } - tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); - tcg_temp_free(tmp); - } - break; - - case 2: /*LSAI*/ -#define gen_load_store(type, shift) do { \ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - \ - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ - if (shift) { \ - gen_load_store_alignment(dc, shift, addr, false); \ - } \ - tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - switch (RRI8_R) { - case 0: /*L8UI*/ - gen_load_store(ld8u, 0); - break; - - case 1: /*L16UI*/ - gen_load_store(ld16u, 1); - break; - - case 2: /*L32I*/ - gen_load_store(ld32u, 2); - break; - - case 4: /*S8I*/ - gen_load_store(st8, 0); - break; - - case 5: /*S16I*/ - gen_load_store(st16, 1); - break; - - case 6: /*S32I*/ - gen_load_store(st32, 2); - break; - -#define gen_dcache_hit_test(w, shift) do { \ - if (gen_window_check1(dc, RRI##w##_S)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - TCGv_i32 res = tcg_temp_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ - RRI##w##_IMM##w << shift); \ - tcg_gen_qemu_ld8u(res, addr, dc->cring); \ - tcg_temp_free(addr); \ - tcg_temp_free(res); \ - } \ - } while (0) - -#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) -#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) - - case 7: /*CACHEc*/ - if (RRI8_T < 8) { - HAS_OPTION(XTENSA_OPTION_DCACHE); - } - - switch (RRI8_T) { - case 0: /*DPFRc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 1: /*DPFWc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 2: /*DPFROc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 3: /*DPFWOc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 4: /*DHWBc*/ - gen_dcache_hit_test8(); - break; - - case 5: /*DHWBIc*/ - gen_dcache_hit_test8(); - break; - - case 6: /*DHIc*/ - if (gen_check_privilege(dc)) { - gen_dcache_hit_test8(); - } - break; - - case 7: /*DIIc*/ - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI8_S); - } - break; - - case 8: /*DCEc*/ - switch (OP1) { - case 0: /*DPFLl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_dcache_hit_test4(); - } - break; - - case 2: /*DHUl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_dcache_hit_test4(); - } - break; - - case 3: /*DIUl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - case 4: /*DIWBc*/ - HAS_OPTION(XTENSA_OPTION_DCACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - case 5: /*DIWBIc*/ - HAS_OPTION(XTENSA_OPTION_DCACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - -#undef gen_dcache_hit_test -#undef gen_dcache_hit_test4 -#undef gen_dcache_hit_test8 - -#define gen_icache_hit_test(w, shift) do { \ - if (gen_window_check1(dc, RRI##w##_S)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - tcg_gen_movi_i32(cpu_pc, dc->pc); \ - tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ - RRI##w##_IMM##w << shift); \ - gen_helper_itlb_hit_test(cpu_env, addr); \ - tcg_temp_free(addr); \ - }\ - } while (0) - -#define gen_icache_hit_test4() gen_icache_hit_test(4, 4) -#define gen_icache_hit_test8() gen_icache_hit_test(8, 2) - - case 12: /*IPFc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - gen_window_check1(dc, RRI8_S); - break; - - case 13: /*ICEc*/ - switch (OP1) { - case 0: /*IPFLl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_icache_hit_test4(); - } - break; - - case 2: /*IHUl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_icache_hit_test4(); - } - break; - - case 3: /*IIUl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 14: /*IHIc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - gen_icache_hit_test8(); - break; - - case 15: /*IIIc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI8_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - -#undef gen_icache_hit_test -#undef gen_icache_hit_test4 -#undef gen_icache_hit_test8 - - case 9: /*L16SI*/ - gen_load_store(ld16s, 1); - break; -#undef gen_load_store - - case 10: /*MOVI*/ - if (gen_window_check1(dc, RRI8_T)) { - tcg_gen_movi_i32(cpu_R[RRI8_T], - RRI8_IMM8 | (RRI8_S << 8) | - ((RRI8_S & 0x8) ? 0xfffff000 : 0)); - } - break; - -#define gen_load_store_no_hw_align(type) do { \ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ - TCGv_i32 addr = tcg_temp_local_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ - gen_load_store_alignment(dc, 2, addr, true); \ - tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - case 11: /*L32AIy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); - gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ - break; - - case 12: /*ADDI*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); - } - break; - - case 13: /*ADDMI*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], - RRI8_IMM8_SE << 8); - } - break; - - case 14: /*S32C1Iy*/ - HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGLabel *label = gen_new_label(); - TCGv_i32 tmp = tcg_temp_local_new_i32(); - TCGv_i32 addr = tcg_temp_local_new_i32(); - TCGv_i32 tpc; - - tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); - gen_load_store_alignment(dc, 2, addr, true); - - tpc = tcg_const_i32(dc->pc); - gen_helper_check_atomctl(cpu_env, tpc, addr); - tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); - tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], - cpu_SR[SCOMPARE1], label); - - tcg_gen_qemu_st32(tmp, addr, dc->cring); - - gen_set_label(label); - tcg_temp_free(tpc); - tcg_temp_free(addr); - tcg_temp_free(tmp); - } - break; - - case 15: /*S32RIy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); - gen_load_store_no_hw_align(st32); /*TODO release?*/ - break; -#undef gen_load_store_no_hw_align - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*LSCIp*/ - switch (RRI8_R) { - case 0: /*LSIf*/ - case 4: /*SSIf*/ - case 8: /*LSIUf*/ - case 12: /*SSIUf*/ - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - if (gen_window_check1(dc, RRI8_S) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); - gen_load_store_alignment(dc, 2, addr, false); - if (RRI8_R & 0x4) { - tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); - } - if (RRI8_R & 0x8) { - tcg_gen_mov_i32(cpu_R[RRI8_S], addr); - } - tcg_temp_free(addr); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 4: /*MAC16d*/ - HAS_OPTION(XTENSA_OPTION_MAC16); - { - enum { - MAC16_UMUL = 0x0, - MAC16_MUL = 0x4, - MAC16_MULA = 0x8, - MAC16_MULS = 0xc, - MAC16_NONE = 0xf, - } op = OP1 & 0xc; - bool is_m1_sr = (OP2 & 0x3) == 2; - bool is_m2_sr = (OP2 & 0xc) == 0; - uint32_t ld_offset = 0; - - if (OP2 > 9) { - RESERVED(); - } - - switch (OP2 & 2) { - case 0: /*MACI?/MACC?*/ - is_m1_sr = true; - ld_offset = (OP2 & 1) ? -4 : 4; - - if (OP2 >= 8) { /*MACI/MACC*/ - if (OP1 == 0) { /*LDINC/LDDEC*/ - op = MAC16_NONE; - } else { - RESERVED(); - } - } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ - RESERVED(); - } - break; - - case 2: /*MACD?/MACA?*/ - if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ - RESERVED(); - } - break; - } - - if (op != MAC16_NONE) { - if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) { - break; - } - if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) { - break; - } - } - - if (ld_offset && !gen_window_check1(dc, RRR_S)) { - break; - } - - { - TCGv_i32 vaddr = tcg_temp_new_i32(); - TCGv_i32 mem32 = tcg_temp_new_i32(); - - if (ld_offset) { - tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); - gen_load_store_alignment(dc, 2, vaddr, false); - tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); - } - if (op != MAC16_NONE) { - TCGv_i32 m1 = gen_mac16_m( - is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], - OP1 & 1, op == MAC16_UMUL); - TCGv_i32 m2 = gen_mac16_m( - is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], - OP1 & 2, op == MAC16_UMUL); - - if (op == MAC16_MUL || op == MAC16_UMUL) { - tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); - if (op == MAC16_UMUL) { - tcg_gen_movi_i32(cpu_SR[ACCHI], 0); - } else { - tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); - } - } else { - TCGv_i32 lo = tcg_temp_new_i32(); - TCGv_i32 hi = tcg_temp_new_i32(); - - tcg_gen_mul_i32(lo, m1, m2); - tcg_gen_sari_i32(hi, lo, 31); - if (op == MAC16_MULA) { - tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], - cpu_SR[ACCLO], cpu_SR[ACCHI], - lo, hi); - } else { - tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], - cpu_SR[ACCLO], cpu_SR[ACCHI], - lo, hi); - } - tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); - } - tcg_temp_free(m1); - tcg_temp_free(m2); - } - if (ld_offset) { - tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); - tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); - } - tcg_temp_free(vaddr); - tcg_temp_free(mem32); - } - } - break; - - case 5: /*CALLN*/ - switch (CALL_N) { - case 0: /*CALL0*/ - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); - gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); - break; - - case 1: /*CALL4w*/ - case 2: /*CALL8w*/ - case 3: /*CALL12w*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_window_check1(dc, CALL_N << 2)) { - gen_callwi(dc, CALL_N, - (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); - } - break; - } - break; - - case 6: /*SI*/ - switch (CALL_N) { - case 0: /*J*/ - gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); - break; - - case 1: /*BZ*/ - if (gen_window_check1(dc, BRI12_S)) { - static const TCGCond cond[] = { - TCG_COND_EQ, /*BEQZ*/ - TCG_COND_NE, /*BNEZ*/ - TCG_COND_LT, /*BLTZ*/ - TCG_COND_GE, /*BGEZ*/ - }; - - gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, - 4 + BRI12_IMM12_SE); - } - break; - - case 2: /*BI0*/ - if (gen_window_check1(dc, BRI8_S)) { - static const TCGCond cond[] = { - TCG_COND_EQ, /*BEQI*/ - TCG_COND_NE, /*BNEI*/ - TCG_COND_LT, /*BLTI*/ - TCG_COND_GE, /*BGEI*/ - }; - - gen_brcondi(dc, cond[BRI8_M & 3], - cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); - } - break; - - case 3: /*BI1*/ - switch (BRI8_M) { - case 0: /*ENTRYw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 pc = tcg_const_i32(dc->pc); - TCGv_i32 s = tcg_const_i32(BRI12_S); - TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); - gen_helper_entry(cpu_env, pc, s, imm); - tcg_temp_free(imm); - tcg_temp_free(s); - tcg_temp_free(pc); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - } - break; - - case 1: /*B1*/ - switch (BRI8_R) { - case 0: /*BFp*/ - case 1: /*BTp*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); - gen_brcondi(dc, - BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, - tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 8: /*LOOP*/ - case 9: /*LOOPNEZ*/ - case 10: /*LOOPGTZ*/ - HAS_OPTION(XTENSA_OPTION_LOOP); - if (gen_window_check1(dc, RRI8_S)) { - uint32_t lend = dc->pc + RRI8_IMM8 + 4; - TCGv_i32 tmp = tcg_const_i32(lend); - - tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); - tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); - gen_helper_wsr_lend(cpu_env, tmp); - tcg_temp_free(tmp); - - if (BRI8_R > 8) { - TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32( - BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, - cpu_R[RRI8_S], 0, label); - gen_jumpi(dc, lend, 1); - gen_set_label(label); - } - - gen_jumpi(dc, dc->next_pc, 0); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 2: /*BLTUI*/ - case 3: /*BGEUI*/ - if (gen_window_check1(dc, BRI8_S)) { - gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, - cpu_R[BRI8_S], B4CONSTU[BRI8_R], - 4 + BRI8_IMM8_SE); - } - break; - } - break; + dc->next_pc = dc->pc + len; + for (i = 1; i < len; ++i) { + b[i] = cpu_ldub_code(env, dc->pc + i); + } + xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); + fmt = xtensa_format_decode(isa, dc->insnbuf); + if (fmt == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unrecognized instruction format (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; + } + slots = xtensa_format_num_slots(isa, fmt); + for (slot = 0; slot < slots; ++slot) { + xtensa_opcode opc; + unsigned opnd, vopnd, opnds; + uint32_t raw_arg[MAX_OPCODE_ARGS]; + uint32_t arg[MAX_OPCODE_ARGS]; + XtensaOpcodeOps *ops; + + dc->raw_arg = raw_arg; + + xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); + opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); + if (opc == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unrecognized opcode in slot %d (pc = %08x)\n", + slot, dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - break; - - case 7: /*B*/ - { - TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; - - switch (RRI8_R & 7) { - case 0: /*BNONE*/ /*BANY*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 1: /*BEQ*/ /*BNE*/ - case 2: /*BLT*/ /*BGE*/ - case 3: /*BLTU*/ /*BGEU*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - static const TCGCond cond[] = { - [1] = TCG_COND_EQ, - [2] = TCG_COND_LT, - [3] = TCG_COND_LTU, - [9] = TCG_COND_NE, - [10] = TCG_COND_GE, - [11] = TCG_COND_GEU, - }; - gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], - 4 + RRI8_IMM8_SE); + opnds = xtensa_opcode_num_operands(isa, opc); + + for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + if (xtensa_operand_is_visible(isa, opc, opnd)) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + raw_arg[vopnd] = v; + if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { + xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); } - break; - - case 4: /*BALL*/ /*BNALL*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); - gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], - 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 5: /*BBC*/ /*BBS*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { -#ifdef TARGET_WORDS_BIGENDIAN - TCGv_i32 bit = tcg_const_i32(0x80000000); -#else - TCGv_i32 bit = tcg_const_i32(0x00000001); -#endif - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_shr_i32(bit, bit, tmp); -#else - tcg_gen_shl_i32(bit, bit, tmp); -#endif - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - tcg_temp_free(bit); - } - break; - - case 6: /*BBCI*/ /*BBSI*/ - case 7: - if (gen_window_check1(dc, RRI8_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], -#ifdef TARGET_WORDS_BIGENDIAN - 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); -#else - 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); -#endif - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - + arg[vopnd] = v; + ++vopnd; } } - break; - -#define gen_narrow_load_store(type) do { \ - if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ - gen_load_store_alignment(dc, 2, addr, false); \ - tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - case 8: /*L32I.Nn*/ - gen_narrow_load_store(ld32u); - break; - - case 9: /*S32I.Nn*/ - gen_narrow_load_store(st32); - break; -#undef gen_narrow_load_store - - case 10: /*ADD.Nn*/ - if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) { - tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); - } - break; - - case 11: /*ADDI.Nn*/ - if (gen_window_check2(dc, RRRN_R, RRRN_S)) { - tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], - RRRN_T ? RRRN_T : -1); - } - break; - - case 12: /*ST2n*/ - if (!gen_window_check1(dc, RRRN_S)) { - break; - } - if (RRRN_T < 8) { /*MOVI.Nn*/ - tcg_gen_movi_i32(cpu_R[RRRN_S], - RRRN_R | (RRRN_T << 4) | - ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); - } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ - TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; - - gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, - 4 + (RRRN_R | ((RRRN_T & 3) << 4))); - } - break; - - case 13: /*ST3n*/ - switch (RRRN_R) { - case 0: /*MOV.Nn*/ - if (gen_window_check2(dc, RRRN_S, RRRN_T)) { - tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); - } - break; - - case 15: /*S3*/ - switch (RRRN_T) { - case 0: /*RET.Nn*/ - gen_jump(dc, cpu_R[0]); - break; - - case 1: /*RETW.Nn*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 2: /*BREAK.Nn*/ - HAS_OPTION(XTENSA_OPTION_DEBUG); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_BN); - } - break; - - case 3: /*NOP.Nn*/ - break; - - case 6: /*ILL.Nn*/ - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; + ops = dc->config->opcode_ops[opc]; + if (ops) { + ops->translate(dc, arg, ops->par); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "unimplemented opcode '%s' in slot %d (pc = %08x)\n", + xtensa_opcode_name(isa, opc), slot, dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - break; - - default: /*reserved*/ - RESERVED(); - break; } - if (dc->is_jmp == DISAS_NEXT) { gen_check_loop_end(dc, 0); } dc->pc = dc->next_pc; - - return; - -invalid_opcode: - qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); -#undef HAS_OPTION } static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) { uint8_t b0 = cpu_ldub_code(env, dc->pc); - return xtensa_op0_insn_len(OP0); + return xtensa_op0_insn_len(dc, b0); } static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) @@ -3151,7 +1071,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); - init_litbase(&dc); + if (dc.config->isa) { + dc.insnbuf = xtensa_insnbuf_alloc(dc.config->isa); + dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); + } + init_sar_tracker(&dc); if (dc.icount) { dc.next_icount = tcg_temp_local_new_i32(); @@ -3226,11 +1150,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && !tcg_op_buf_full()); done: - reset_litbase(&dc); reset_sar_tracker(&dc); if (dc.icount) { tcg_temp_free(dc.next_icount); } + if (dc.config->isa) { + xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); + xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); + } if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); @@ -3312,3 +1239,3612 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, { env->pc = data[0]; } + +static int compare_opcode_ops(const void *a, const void *b) +{ + return strcmp((const char *)a, + ((const XtensaOpcodeOps *)b)->name); +} + +XtensaOpcodeOps * +xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, + const char *name) +{ + XtensaOpcodeOps *ops; + + ops = bsearch(name, t->opcode, t->num_opcodes, + sizeof(XtensaOpcodeOps), compare_opcode_ops); + return ops; +} + +static void translate_abs(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 neg = tcg_temp_new_i32(); + + tcg_gen_neg_i32(neg, cpu_R[arg[1]]); + tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], + cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); + tcg_temp_free(neg); + tcg_temp_free(zero); + } +} + +static void translate_add(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_addi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_addx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); + tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_temp_free(tmp); + } +} + +static void translate_all(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + uint32_t shift = par[1]; + TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_and_i32(tmp, cpu_SR[BR], mask); + if (par[0]) { + tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); + } else { + tcg_gen_add_i32(tmp, tmp, mask); + } + tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); + tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], + tmp, arg[0], 1); + tcg_temp_free(mask); + tcg_temp_free(tmp); +} + +static void translate_and(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_ball(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_bany(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_b(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_bb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { +#ifdef TARGET_WORDS_BIGENDIAN + TCGv_i32 bit = tcg_const_i32(0x80000000u); +#else + TCGv_i32 bit = tcg_const_i32(0x00000001u); +#endif + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_shr_i32(bit, bit, tmp); +#else + tcg_gen_shl_i32(bit, bit, tmp); +#endif + tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + tcg_temp_free(bit); + } +} + +static void translate_bbi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); +#else + tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); +#endif + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_bi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); + } +} + +static void translate_bz(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); + } +} + +enum { + BOOLEAN_AND, + BOOLEAN_ANDC, + BOOLEAN_OR, + BOOLEAN_ORC, + BOOLEAN_XOR, +}; + +static void translate_boolean(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { + [BOOLEAN_AND] = tcg_gen_and_i32, + [BOOLEAN_ANDC] = tcg_gen_andc_i32, + [BOOLEAN_OR] = tcg_gen_or_i32, + [BOOLEAN_ORC] = tcg_gen_orc_i32, + [BOOLEAN_XOR] = tcg_gen_xor_i32, + }; + + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i32 tmp2 = tcg_temp_new_i32(); + + tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); + tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); + op[par[0]](tmp1, tmp1, tmp2); + tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); +} + +static void translate_bp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); + gen_brcondi(dc, par[0], tmp, 0, arg[1]); + tcg_temp_free(tmp); +} + +static void translate_break(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (dc->debug) { + gen_debug_exception(dc, par[0]); + } +} + +static void translate_call0(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + gen_jumpi(dc, arg[0], 0); +} + +static void translate_callw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, par[0] << 2)) { + gen_callwi(dc, par[0], arg[0], 0); + } +} + +static void translate_callx0(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + gen_jump(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_callxw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], par[0] << 2)) { + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + gen_callw(dc, par[0], tmp); + tcg_temp_free(tmp); + } +} + +static void translate_clamps(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); + TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); + + tcg_gen_movcond_i32(TCG_COND_GT, tmp1, + cpu_R[arg[1]], tmp1, cpu_R[arg[1]], tmp1); + tcg_gen_movcond_i32(TCG_COND_LT, cpu_R[arg[0]], + tmp1, tmp2, tmp1, tmp2); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + } +} + +static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); +} + +static void translate_const16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 c = tcg_const_i32(arg[1]); + + tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); + tcg_temp_free(c); + } +} + +/* par[0]: privileged, par[1]: check memory access */ +static void translate_dcache(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if ((!par[0] || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0]) && par[1]) { + TCGv_i32 addr = tcg_temp_new_i32(); + TCGv_i32 res = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_qemu_ld8u(res, addr, dc->cring); + tcg_temp_free(addr); + tcg_temp_free(res); + } +} + +static void translate_depbits(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], + arg[2], arg[3]); + } +} + +static void translate_entry(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 pc = tcg_const_i32(dc->pc); + TCGv_i32 s = tcg_const_i32(arg[0]); + TCGv_i32 imm = tcg_const_i32(arg[1]); + gen_helper_entry(cpu_env, pc, s, imm); + tcg_temp_free(imm); + tcg_temp_free(s); + tcg_temp_free(pc); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + +static void translate_extui(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + int maskimm = (1 << arg[3]) - 1; + + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); + tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); + tcg_temp_free(tmp); + } +} + +/* par[0]: privileged, par[1]: check memory access */ +static void translate_icache(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if ((!par[0] || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0]) && par[1]) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + gen_helper_itlb_hit_test(cpu_env, addr); + tcg_temp_free(addr); + } +} + +static void translate_itlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check1(dc, arg[0])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); + /* This could change memory mapping, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + tcg_temp_free(dtlb); + } +} + +static void translate_ill(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); +} + +static void translate_j(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_jumpi(dc, arg[0], 0); +} + +static void translate_jx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_jump(dc, cpu_R[arg[0]]); + } +} + +static void translate_l32e(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_temp_free(addr); + } +} + +static void translate_ldst(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + if (par[0] & MO_SIZE) { + gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); + } + if (par[2]) { + tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + } else { + tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + } + tcg_temp_free(addr); + } +} + +static void translate_l32r(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp; + + if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); + } else { + tmp = tcg_const_i32(arg[1]); + } + tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); + tcg_temp_free(tmp); + } +} + +static void translate_loop(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + uint32_t lend = arg[1]; + TCGv_i32 tmp = tcg_const_i32(lend); + + tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); + tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); + gen_helper_wsr_lend(cpu_env, tmp); + tcg_temp_free(tmp); + + if (par[0] != TCG_COND_NEVER) { + TCGLabel *label = gen_new_label(); + tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); + gen_jumpi(dc, lend, 1); + gen_set_label(label); + } + + gen_jumpi(dc, dc->next_pc, 0); + } +} + +enum { + MAC16_UMUL, + MAC16_MUL, + MAC16_MULA, + MAC16_MULS, + MAC16_NONE, +}; + +enum { + MAC16_LL, + MAC16_HL, + MAC16_LH, + MAC16_HH, + + MAC16_HX = 0x1, + MAC16_XH = 0x2, +}; + +enum { + MAC16_AA, + MAC16_AD, + MAC16_DA, + MAC16_DD, + + MAC16_XD = 0x1, + MAC16_DX = 0x2, +}; + +static void translate_mac16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + int op = par[0]; + bool is_m1_sr = par[1] & MAC16_DX; + bool is_m2_sr = par[1] & MAC16_XD; + unsigned half = par[2]; + uint32_t ld_offset = par[3]; + unsigned off = ld_offset ? 2 : 0; + uint32_t ar[3] = {0}; + unsigned n_ar = 0; + + if (op != MAC16_NONE) { + if (!is_m1_sr) { + ar[n_ar++] = arg[off]; + } + if (!is_m2_sr) { + ar[n_ar++] = arg[off + 1]; + } + } + + if (ld_offset) { + ar[n_ar++] = arg[1]; + } + + if (gen_window_check3(dc, ar[0], ar[1], ar[2])) { + TCGv_i32 vaddr = tcg_temp_new_i32(); + TCGv_i32 mem32 = tcg_temp_new_i32(); + + if (ld_offset) { + tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); + gen_load_store_alignment(dc, 2, vaddr, false); + tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); + } + if (op != MAC16_NONE) { + TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? + cpu_SR[MR + arg[off]] : + cpu_R[arg[off]], + half & MAC16_HX, op == MAC16_UMUL); + TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? + cpu_SR[MR + arg[off + 1]] : + cpu_R[arg[off + 1]], + half & MAC16_XH, op == MAC16_UMUL); + + if (op == MAC16_MUL || op == MAC16_UMUL) { + tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); + if (op == MAC16_UMUL) { + tcg_gen_movi_i32(cpu_SR[ACCHI], 0); + } else { + tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); + } + } else { + TCGv_i32 lo = tcg_temp_new_i32(); + TCGv_i32 hi = tcg_temp_new_i32(); + + tcg_gen_mul_i32(lo, m1, m2); + tcg_gen_sari_i32(hi, lo, 31); + if (op == MAC16_MULA) { + tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], + cpu_SR[ACCLO], cpu_SR[ACCHI], + lo, hi); + } else { + tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], + cpu_SR[ACCLO], cpu_SR[ACCHI], + lo, hi); + } + tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); + } + tcg_temp_free(m1); + tcg_temp_free(m2); + } + if (ld_offset) { + tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); + tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); + } + tcg_temp_free(vaddr); + tcg_temp_free(mem32); + } +} + +static void translate_minmax(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_mov(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_movcond(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], + cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_temp_free(zero); + } +} + +static void translate_movi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); + } +} + +static void translate_movp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_R[arg[0]], tmp, zero, + cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } +} + +static void translate_movsp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 pc = tcg_const_i32(dc->pc); + gen_helper_movsp(cpu_env, pc); + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_temp_free(pc); + } +} + +static void translate_mul16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 v1 = tcg_temp_new_i32(); + TCGv_i32 v2 = tcg_temp_new_i32(); + + if (par[0]) { + tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); + tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); + } else { + tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); + tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); + } + tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); + tcg_temp_free(v2); + tcg_temp_free(v1); + } +} + +static void translate_mull(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_mulh(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 lo = tcg_temp_new(); + + if (par[0]) { + tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } + tcg_temp_free(lo); + } +} + +static void translate_neg(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_nop(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ +} + +static void translate_nsa(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_nsau(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); + } +} + +static void translate_or(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_ptlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + tcg_temp_free(dtlb); + } +} + +static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) +{ + TCGLabel *label = gen_new_label(); + + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); + gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); + gen_set_label(label); +} + +static void translate_quos(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGLabel *label1 = gen_new_label(); + TCGLabel *label2 = gen_new_label(); + + gen_zero_check(dc, arg); + + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, + label1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, + label1); + tcg_gen_movi_i32(cpu_R[arg[0]], + par[0] ? 0x80000000 : 0); + tcg_gen_br(label2); + gen_set_label(label1); + if (par[0]) { + tcg_gen_div_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_rem_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } + gen_set_label(label2); + } +} + +static void translate_quou(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + gen_zero_check(dc, arg); + if (par[0]) { + tcg_gen_divu_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_remu_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } + } +} + +static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_movi_i32(cpu_R[arg[0]], 0); + } +} + +static void translate_rer(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); + } +} + +static void translate_ret(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_jump(dc, cpu_R[0]); +} + +static void translate_retw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_const_i32(dc->pc); + gen_helper_retw(tmp, cpu_env, tmp); + gen_jump(dc, tmp); + tcg_temp_free(tmp); +} + +static void translate_rfde(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); + } +} + +static void translate_rfe(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); + } +} + +static void translate_rfi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); + } +} + +static void translate_rfw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + TCGv_i32 tmp = tcg_const_i32(1); + + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); + + if (par[0]) { + tcg_gen_andc_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } else { + tcg_gen_or_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } + + gen_helper_restore_owb(cpu_env); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); + + tcg_temp_free(tmp); + } +} + +static void translate_rotw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + TCGv_i32 tmp = tcg_const_i32(arg[0]); + gen_helper_rotw(cpu_env, tmp); + tcg_temp_free(tmp); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + } +} + +static void translate_rsil(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check1(dc, arg[0])) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); + tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); + gen_check_interrupts(dc); + gen_jumpi_check_loop_end(dc, 0); + } +} + +static void translate_rsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_R) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + if (gen_rsr(dc, cpu_R[arg[0]], par[0])) { + gen_jumpi_check_loop_end(dc, 0); + } + } +} + +static void translate_rtlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, + TCGv_i32 a2) = { + gen_helper_rtlb0, + gen_helper_rtlb1, + }; + + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + tcg_temp_free(dtlb); + } +} + +static void translate_rur(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + if (uregnames[par[0]].name) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); + } else { + qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", par[0]); + } + } +} + +static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); +} + +static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGLabel *label = gen_new_label(); + TCGv_i32 tmp = tcg_temp_local_new_i32(); + TCGv_i32 addr = tcg_temp_local_new_i32(); + TCGv_i32 tpc; + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, true); + + tpc = tcg_const_i32(dc->pc); + gen_helper_check_atomctl(cpu_env, tpc, addr); + tcg_gen_qemu_ld32u(cpu_R[arg[0]], addr, dc->cring); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[arg[0]], + cpu_SR[SCOMPARE1], label); + + tcg_gen_qemu_st32(tmp, addr, dc->cring); + + gen_set_label(label); + tcg_temp_free(tpc); + tcg_temp_free(addr); + tcg_temp_free(tmp); + } +} + +static void translate_s32e(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_temp_free(addr); + } +} + +static void translate_salt(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_setcond_i32(par[0], + cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_sext(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + int shift = 31 - arg[2]; + + if (shift == 24) { + tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } else if (shift == 16) { + tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } else { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); + tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); + tcg_temp_free(tmp); + } + } +} + +static void translate_simcall(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (semihosting_enabled()) { + if (gen_check_privilege(dc)) { + gen_helper_simcall(cpu_env); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + } +} + +/* + * Note: 64 bit ops are used here solely because SAR values + * have range 0..63 + */ +#define gen_shift_reg(cmd, reg) do { \ + TCGv_i64 tmp = tcg_temp_new_i64(); \ + tcg_gen_extu_i32_i64(tmp, reg); \ + tcg_gen_##cmd##_i64(v, v, tmp); \ + tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ + tcg_temp_free_i64(v); \ + tcg_temp_free_i64(tmp); \ + } while (0) + +#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) + +static void translate_sll(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + TCGv_i32 s = tcg_const_i32(32); + tcg_gen_sub_i32(s, s, cpu_SR[SAR]); + tcg_gen_andi_i32(s, s, 0x3f); + tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + gen_shift_reg(shl, s); + tcg_temp_free(s); + } + } +} + +static void translate_slli(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (arg[2] == 32) { + qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined", + arg[0], arg[1]); + } + tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); + } +} + +static void translate_sra(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); + gen_shift(sar); + } + } +} + +static void translate_srai(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_src(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); + gen_shift(shr); + } +} + +static void translate_srl(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + gen_shift(shr); + } + } +} + +#undef gen_shift +#undef gen_shift_reg + +static void translate_srli(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + gen_left_shift_sar(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + gen_right_shift_sar(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_ssai(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_const_i32(arg[0]); + gen_right_shift_sar(dc, tmp); + tcg_temp_free(tmp); +} + +static void translate_ssl(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_left_shift_sar(dc, cpu_R[arg[0]]); + } +} + +static void translate_ssr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_right_shift_sar(dc, cpu_R[arg[0]]); + } +} + +static void translate_sub(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_subx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); + tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_temp_free(tmp); + } +} + +static void translate_syscall(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_exception_cause(dc, SYSCALL_CAUSE); +} + +static void translate_waiti(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + gen_waiti(dc, arg[0]); + } +} + +static void translate_wtlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); + /* This could change memory mapping, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + tcg_temp_free(dtlb); + } +} + +static void translate_wer(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_wsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_W) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + gen_wsr(dc, par[0], cpu_R[arg[0]]); + } +} + +static void translate_wur(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + if (uregnames[par[0]].name) { + gen_wur(par[0], cpu_R[arg[0]]); + } else { + qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", par[0]); + } + } +} + +static void translate_xor(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_xsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_X) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + bool rsr_end, wsr_end; + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + rsr_end = gen_rsr(dc, cpu_R[arg[0]], par[0]); + wsr_end = gen_wsr(dc, par[0], tmp); + tcg_temp_free(tmp); + if (rsr_end && !wsr_end) { + gen_jumpi_check_loop_end(dc, 0); + } + } +} + +static const XtensaOpcodeOps core_ops[] = { + { + .name = "abs", + .translate = translate_abs, + }, { + .name = "add", + .translate = translate_add, + }, { + .name = "add.n", + .translate = translate_add, + }, { + .name = "addi", + .translate = translate_addi, + }, { + .name = "addi.n", + .translate = translate_addi, + }, { + .name = "addmi", + .translate = translate_addi, + }, { + .name = "addx2", + .translate = translate_addx, + .par = (const uint32_t[]){1}, + }, { + .name = "addx4", + .translate = translate_addx, + .par = (const uint32_t[]){2}, + }, { + .name = "addx8", + .translate = translate_addx, + .par = (const uint32_t[]){3}, + }, { + .name = "all4", + .translate = translate_all, + .par = (const uint32_t[]){true, 4}, + }, { + .name = "all8", + .translate = translate_all, + .par = (const uint32_t[]){true, 8}, + }, { + .name = "and", + .translate = translate_and, + }, { + .name = "andb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_AND}, + }, { + .name = "andbc", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_ANDC}, + }, { + .name = "any4", + .translate = translate_all, + .par = (const uint32_t[]){false, 4}, + }, { + .name = "any8", + .translate = translate_all, + .par = (const uint32_t[]){false, 8}, + }, { + .name = "ball", + .translate = translate_ball, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bany", + .translate = translate_bany, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bbc", + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bbci", + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bbs", + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bbsi", + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "beq", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqi", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqz", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqz.n", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bf", + .translate = translate_bp, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bge", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "bgei", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "bgeu", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "bgeui", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "bgez", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "blt", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "blti", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "bltu", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "bltui", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "bltz", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "bnall", + .translate = translate_ball, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bne", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnei", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnez", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnez.n", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnone", + .translate = translate_bany, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "break", + .translate = translate_break, + .par = (const uint32_t[]){DEBUGCAUSE_BI}, + }, { + .name = "break.n", + .translate = translate_break, + .par = (const uint32_t[]){DEBUGCAUSE_BN}, + }, { + .name = "bt", + .translate = translate_bp, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "call0", + .translate = translate_call0, + }, { + .name = "call12", + .translate = translate_callw, + .par = (const uint32_t[]){3}, + }, { + .name = "call4", + .translate = translate_callw, + .par = (const uint32_t[]){1}, + }, { + .name = "call8", + .translate = translate_callw, + .par = (const uint32_t[]){2}, + }, { + .name = "callx0", + .translate = translate_callx0, + }, { + .name = "callx12", + .translate = translate_callxw, + .par = (const uint32_t[]){3}, + }, { + .name = "callx4", + .translate = translate_callxw, + .par = (const uint32_t[]){1}, + }, { + .name = "callx8", + .translate = translate_callxw, + .par = (const uint32_t[]){2}, + }, { + .name = "clamps", + .translate = translate_clamps, + }, { + .name = "clrb_expstate", + .translate = translate_clrb_expstate, + }, { + .name = "const16", + .translate = translate_const16, + }, { + .name = "depbits", + .translate = translate_depbits, + }, { + .name = "dhi", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dhu", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dhwb", + .translate = translate_dcache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "dhwbi", + .translate = translate_dcache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "dii", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diu", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diwb", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diwbi", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "dpfl", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dpfr", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfro", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfw", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfwo", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dsync", + .translate = translate_nop, + }, { + .name = "entry", + .translate = translate_entry, + }, { + .name = "esync", + .translate = translate_nop, + }, { + .name = "excw", + .translate = translate_nop, + }, { + .name = "extui", + .translate = translate_extui, + }, { + .name = "extw", + .translate = translate_nop, + }, { + .name = "hwwdtlba", + .translate = translate_ill, + }, { + .name = "hwwitlba", + .translate = translate_ill, + }, { + .name = "idtlb", + .translate = translate_itlb, + .par = (const uint32_t[]){true}, + }, { + .name = "ihi", + .translate = translate_icache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "ihu", + .translate = translate_icache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "iii", + .translate = translate_icache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "iitlb", + .translate = translate_itlb, + .par = (const uint32_t[]){false}, + }, { + .name = "iiu", + .translate = translate_icache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ill", + .translate = translate_ill, + }, { + .name = "ill.n", + .translate = translate_ill, + }, { + .name = "ipf", + .translate = translate_icache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "ipfl", + .translate = translate_icache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "isync", + .translate = translate_nop, + }, { + .name = "j", + .translate = translate_j, + }, { + .name = "jx", + .translate = translate_jx, + }, { + .name = "l16si", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TESW, false, false}, + }, { + .name = "l16ui", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUW, false, false}, + }, { + .name = "l32ai", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, true, false}, + }, { + .name = "l32e", + .translate = translate_l32e, + }, { + .name = "l32i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, false}, + }, { + .name = "l32i.n", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, false}, + }, { + .name = "l32r", + .translate = translate_l32r, + }, { + .name = "l8ui", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_UB, false, false}, + }, { + .name = "lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, + }, { + .name = "ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, + }, { + .name = "ldpte", + .translate = translate_ill, + }, { + .name = "loop", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_NEVER}, + }, { + .name = "loopgtz", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_GT}, + }, { + .name = "loopnez", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "max", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "maxu", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "memw", + .translate = translate_nop, + }, { + .name = "min", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "minu", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "mov", + .translate = translate_mov, + }, { + .name = "mov.n", + .translate = translate_mov, + }, { + .name = "moveqz", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movf", + .translate = translate_movp, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movgez", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "movi", + .translate = translate_movi, + }, { + .name = "movi.n", + .translate = translate_movi, + }, { + .name = "movltz", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "movnez", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "movsp", + .translate = translate_movsp, + }, { + .name = "movt", + .translate = translate_movp, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "mul.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "mul.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "mul.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "mul.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "mul.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "mul.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "mul.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "mul.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "mul.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "mul.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "mul.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "mul.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "mul.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "mul.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "mul.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "mul.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mul16s", + .translate = translate_mul16, + .par = (const uint32_t[]){true}, + }, { + .name = "mul16u", + .translate = translate_mul16, + .par = (const uint32_t[]){false}, + }, { + .name = "mula.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "mula.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "mula.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "mula.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "mula.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "mula.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "mula.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "mula.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "mula.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "mula.da.hh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, + }, { + .name = "mula.da.hh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, + }, { + .name = "mula.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "mula.da.hl.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, + }, { + .name = "mula.da.hl.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, + }, { + .name = "mula.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "mula.da.lh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, + }, { + .name = "mula.da.lh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, + }, { + .name = "mula.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "mula.da.ll.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, + }, { + .name = "mula.da.ll.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, + }, { + .name = "mula.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "mula.dd.hh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, + }, { + .name = "mula.dd.hh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, + }, { + .name = "mula.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "mula.dd.hl.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, + }, { + .name = "mula.dd.hl.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, + }, { + .name = "mula.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "mula.dd.lh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, + }, { + .name = "mula.dd.lh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, + }, { + .name = "mula.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mula.dd.ll.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, + }, { + .name = "mula.dd.ll.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, + }, { + .name = "mull", + .translate = translate_mull, + }, { + .name = "muls.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "muls.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "muls.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "muls.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "muls.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "muls.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "muls.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "muls.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "muls.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "muls.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "muls.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "muls.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "muls.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "muls.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "muls.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "muls.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mulsh", + .translate = translate_mulh, + .par = (const uint32_t[]){true}, + }, { + .name = "muluh", + .translate = translate_mulh, + .par = (const uint32_t[]){false}, + }, { + .name = "neg", + .translate = translate_neg, + }, { + .name = "nop", + .translate = translate_nop, + }, { + .name = "nop.n", + .translate = translate_nop, + }, { + .name = "nsa", + .translate = translate_nsa, + }, { + .name = "nsau", + .translate = translate_nsau, + }, { + .name = "or", + .translate = translate_or, + }, { + .name = "orb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_OR}, + }, { + .name = "orbc", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_ORC}, + }, { + .name = "pdtlb", + .translate = translate_ptlb, + .par = (const uint32_t[]){true}, + }, { + .name = "pitlb", + .translate = translate_ptlb, + .par = (const uint32_t[]){false}, + }, { + .name = "quos", + .translate = translate_quos, + .par = (const uint32_t[]){true}, + }, { + .name = "quou", + .translate = translate_quou, + .par = (const uint32_t[]){true}, + }, { + .name = "rdtlb0", + .translate = translate_rtlb, + .par = (const uint32_t[]){true, 0}, + }, { + .name = "rdtlb1", + .translate = translate_rtlb, + .par = (const uint32_t[]){true, 1}, + }, { + .name = "read_impwire", + .translate = translate_read_impwire, + }, { + .name = "rems", + .translate = translate_quos, + .par = (const uint32_t[]){false}, + }, { + .name = "remu", + .translate = translate_quou, + .par = (const uint32_t[]){false}, + }, { + .name = "rer", + .translate = translate_rer, + }, { + .name = "ret", + .translate = translate_ret, + }, { + .name = "ret.n", + .translate = translate_ret, + }, { + .name = "retw", + .translate = translate_retw, + }, { + .name = "retw.n", + .translate = translate_retw, + }, { + .name = "rfdd", + .translate = translate_ill, + }, { + .name = "rfde", + .translate = translate_rfde, + }, { + .name = "rfdo", + .translate = translate_ill, + }, { + .name = "rfe", + .translate = translate_rfe, + }, { + .name = "rfi", + .translate = translate_rfi, + }, { + .name = "rfwo", + .translate = translate_rfw, + .par = (const uint32_t[]){true}, + }, { + .name = "rfwu", + .translate = translate_rfw, + .par = (const uint32_t[]){false}, + }, { + .name = "ritlb0", + .translate = translate_rtlb, + .par = (const uint32_t[]){false, 0}, + }, { + .name = "ritlb1", + .translate = translate_rtlb, + .par = (const uint32_t[]){false, 1}, + }, { + .name = "rotw", + .translate = translate_rotw, + }, { + .name = "rsil", + .translate = translate_rsil, + }, { + .name = "rsr.176", + .translate = translate_rsr, + .par = (const uint32_t[]){176}, + }, { + .name = "rsr.208", + .translate = translate_rsr, + .par = (const uint32_t[]){208}, + }, { + .name = "rsr.acchi", + .translate = translate_rsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "rsr.acclo", + .translate = translate_rsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "rsr.atomctl", + .translate = translate_rsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "rsr.br", + .translate = translate_rsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "rsr.cacheattr", + .translate = translate_rsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "rsr.ccompare0", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "rsr.ccompare1", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "rsr.ccompare2", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "rsr.ccount", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "rsr.configid0", + .translate = translate_rsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "rsr.configid1", + .translate = translate_rsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "rsr.cpenable", + .translate = translate_rsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "rsr.dbreaka0", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "rsr.dbreaka1", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "rsr.dbreakc0", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "rsr.dbreakc1", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "rsr.ddr", + .translate = translate_rsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "rsr.debugcause", + .translate = translate_rsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "rsr.depc", + .translate = translate_rsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "rsr.dtlbcfg", + .translate = translate_rsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "rsr.epc1", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "rsr.epc2", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "rsr.epc3", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "rsr.epc4", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "rsr.epc5", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "rsr.epc6", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "rsr.epc7", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "rsr.eps2", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "rsr.eps3", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "rsr.eps4", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "rsr.eps5", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "rsr.eps6", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "rsr.eps7", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "rsr.exccause", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "rsr.excsave1", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "rsr.excsave2", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "rsr.excsave3", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "rsr.excsave4", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "rsr.excsave5", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "rsr.excsave6", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "rsr.excsave7", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "rsr.excvaddr", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "rsr.ibreaka0", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "rsr.ibreaka1", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "rsr.ibreakenable", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "rsr.icount", + .translate = translate_rsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "rsr.icountlevel", + .translate = translate_rsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "rsr.intclear", + .translate = translate_rsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "rsr.intenable", + .translate = translate_rsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "rsr.interrupt", + .translate = translate_rsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "rsr.intset", + .translate = translate_rsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "rsr.itlbcfg", + .translate = translate_rsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "rsr.lbeg", + .translate = translate_rsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "rsr.lcount", + .translate = translate_rsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "rsr.lend", + .translate = translate_rsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "rsr.litbase", + .translate = translate_rsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "rsr.m0", + .translate = translate_rsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "rsr.m1", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "rsr.m2", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "rsr.m3", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "rsr.memctl", + .translate = translate_rsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "rsr.misc0", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "rsr.misc1", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "rsr.misc2", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "rsr.misc3", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "rsr.prid", + .translate = translate_rsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "rsr.ps", + .translate = translate_rsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "rsr.ptevaddr", + .translate = translate_rsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "rsr.rasid", + .translate = translate_rsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "rsr.sar", + .translate = translate_rsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "rsr.scompare1", + .translate = translate_rsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "rsr.vecbase", + .translate = translate_rsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "rsr.windowbase", + .translate = translate_rsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "rsr.windowstart", + .translate = translate_rsr, + .par = (const uint32_t[]){WINDOW_START}, + }, { + .name = "rsync", + .translate = translate_nop, + }, { + .name = "rur.expstate", + .translate = translate_rur, + .par = (const uint32_t[]){EXPSTATE}, + }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + }, { + .name = "rur.fsr", + .translate = translate_rur, + .par = (const uint32_t[]){FSR}, + }, { + .name = "rur.threadptr", + .translate = translate_rur, + .par = (const uint32_t[]){THREADPTR}, + }, { + .name = "s16i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUW, false, true}, + }, { + .name = "s32c1i", + .translate = translate_s32c1i, + }, { + .name = "s32e", + .translate = translate_s32e, + }, { + .name = "s32i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32i.n", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32nb", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32ri", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, true, true}, + }, { + .name = "s8i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_UB, false, true}, + }, { + .name = "salt", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "saltu", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "setb_expstate", + .translate = translate_setb_expstate, + }, { + .name = "sext", + .translate = translate_sext, + }, { + .name = "simcall", + .translate = translate_simcall, + }, { + .name = "sll", + .translate = translate_sll, + }, { + .name = "slli", + .translate = translate_slli, + }, { + .name = "sra", + .translate = translate_sra, + }, { + .name = "srai", + .translate = translate_srai, + }, { + .name = "src", + .translate = translate_src, + }, { + .name = "srl", + .translate = translate_srl, + }, { + .name = "srli", + .translate = translate_srli, + }, { + .name = "ssa8b", + .translate = translate_ssa8b, + }, { + .name = "ssa8l", + .translate = translate_ssa8l, + }, { + .name = "ssai", + .translate = translate_ssai, + }, { + .name = "ssl", + .translate = translate_ssl, + }, { + .name = "ssr", + .translate = translate_ssr, + }, { + .name = "sub", + .translate = translate_sub, + }, { + .name = "subx2", + .translate = translate_subx, + .par = (const uint32_t[]){1}, + }, { + .name = "subx4", + .translate = translate_subx, + .par = (const uint32_t[]){2}, + }, { + .name = "subx8", + .translate = translate_subx, + .par = (const uint32_t[]){3}, + }, { + .name = "syscall", + .translate = translate_syscall, + }, { + .name = "umul.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "umul.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "umul.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "umul.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "waiti", + .translate = translate_waiti, + }, { + .name = "wdtlb", + .translate = translate_wtlb, + .par = (const uint32_t[]){true}, + }, { + .name = "wer", + .translate = translate_wer, + }, { + .name = "witlb", + .translate = translate_wtlb, + .par = (const uint32_t[]){false}, + }, { + .name = "wrmsk_expstate", + .translate = translate_wrmsk_expstate, + }, { + .name = "wsr.176", + .translate = translate_wsr, + .par = (const uint32_t[]){176}, + }, { + .name = "wsr.208", + .translate = translate_wsr, + .par = (const uint32_t[]){208}, + }, { + .name = "wsr.acchi", + .translate = translate_wsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "wsr.acclo", + .translate = translate_wsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "wsr.atomctl", + .translate = translate_wsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "wsr.br", + .translate = translate_wsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "wsr.cacheattr", + .translate = translate_wsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "wsr.ccompare0", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "wsr.ccompare1", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "wsr.ccompare2", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "wsr.ccount", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "wsr.configid0", + .translate = translate_wsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "wsr.configid1", + .translate = translate_wsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "wsr.cpenable", + .translate = translate_wsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "wsr.dbreaka0", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "wsr.dbreaka1", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "wsr.dbreakc0", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "wsr.dbreakc1", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "wsr.ddr", + .translate = translate_wsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "wsr.debugcause", + .translate = translate_wsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "wsr.depc", + .translate = translate_wsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "wsr.dtlbcfg", + .translate = translate_wsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "wsr.epc1", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "wsr.epc2", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "wsr.epc3", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "wsr.epc4", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "wsr.epc5", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "wsr.epc6", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "wsr.epc7", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "wsr.eps2", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "wsr.eps3", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "wsr.eps4", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "wsr.eps5", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "wsr.eps6", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "wsr.eps7", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "wsr.exccause", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "wsr.excsave1", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "wsr.excsave2", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "wsr.excsave3", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "wsr.excsave4", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "wsr.excsave5", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "wsr.excsave6", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "wsr.excsave7", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "wsr.excvaddr", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "wsr.ibreaka0", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "wsr.ibreaka1", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "wsr.ibreakenable", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "wsr.icount", + .translate = translate_wsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "wsr.icountlevel", + .translate = translate_wsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "wsr.intclear", + .translate = translate_wsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "wsr.intenable", + .translate = translate_wsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "wsr.interrupt", + .translate = translate_wsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "wsr.intset", + .translate = translate_wsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "wsr.itlbcfg", + .translate = translate_wsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "wsr.lbeg", + .translate = translate_wsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "wsr.lcount", + .translate = translate_wsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "wsr.lend", + .translate = translate_wsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "wsr.litbase", + .translate = translate_wsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "wsr.m0", + .translate = translate_wsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "wsr.m1", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "wsr.m2", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "wsr.m3", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "wsr.memctl", + .translate = translate_wsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "wsr.misc0", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "wsr.misc1", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "wsr.misc2", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "wsr.misc3", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "wsr.mmid", + .translate = translate_wsr, + .par = (const uint32_t[]){MMID}, + }, { + .name = "wsr.prid", + .translate = translate_wsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "wsr.ps", + .translate = translate_wsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "wsr.ptevaddr", + .translate = translate_wsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "wsr.rasid", + .translate = translate_wsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "wsr.sar", + .translate = translate_wsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "wsr.scompare1", + .translate = translate_wsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "wsr.vecbase", + .translate = translate_wsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "wsr.windowbase", + .translate = translate_wsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "wsr.windowstart", + .translate = translate_wsr, + .par = (const uint32_t[]){WINDOW_START}, + }, { + .name = "wur.expstate", + .translate = translate_wur, + .par = (const uint32_t[]){EXPSTATE}, + }, { + .name = "wur.fcr", + .translate = translate_wur, + .par = (const uint32_t[]){FCR}, + }, { + .name = "wur.fsr", + .translate = translate_wur, + .par = (const uint32_t[]){FSR}, + }, { + .name = "wur.threadptr", + .translate = translate_wur, + .par = (const uint32_t[]){THREADPTR}, + }, { + .name = "xor", + .translate = translate_xor, + }, { + .name = "xorb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_XOR}, + }, { + .name = "xsr.176", + .translate = translate_xsr, + .par = (const uint32_t[]){176}, + }, { + .name = "xsr.208", + .translate = translate_xsr, + .par = (const uint32_t[]){208}, + }, { + .name = "xsr.acchi", + .translate = translate_xsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "xsr.acclo", + .translate = translate_xsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "xsr.atomctl", + .translate = translate_xsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "xsr.br", + .translate = translate_xsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "xsr.cacheattr", + .translate = translate_xsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "xsr.ccompare0", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "xsr.ccompare1", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "xsr.ccompare2", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "xsr.ccount", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "xsr.configid0", + .translate = translate_xsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "xsr.configid1", + .translate = translate_xsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "xsr.cpenable", + .translate = translate_xsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "xsr.dbreaka0", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "xsr.dbreaka1", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "xsr.dbreakc0", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "xsr.dbreakc1", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "xsr.ddr", + .translate = translate_xsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "xsr.debugcause", + .translate = translate_xsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "xsr.depc", + .translate = translate_xsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "xsr.dtlbcfg", + .translate = translate_xsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "xsr.epc1", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "xsr.epc2", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "xsr.epc3", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "xsr.epc4", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "xsr.epc5", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "xsr.epc6", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "xsr.epc7", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "xsr.eps2", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "xsr.eps3", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "xsr.eps4", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "xsr.eps5", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "xsr.eps6", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "xsr.eps7", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "xsr.exccause", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "xsr.excsave1", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "xsr.excsave2", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "xsr.excsave3", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "xsr.excsave4", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "xsr.excsave5", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "xsr.excsave6", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "xsr.excsave7", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "xsr.excvaddr", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "xsr.ibreaka0", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "xsr.ibreaka1", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "xsr.ibreakenable", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "xsr.icount", + .translate = translate_xsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "xsr.icountlevel", + .translate = translate_xsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "xsr.intclear", + .translate = translate_xsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "xsr.intenable", + .translate = translate_xsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "xsr.interrupt", + .translate = translate_xsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "xsr.intset", + .translate = translate_xsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "xsr.itlbcfg", + .translate = translate_xsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "xsr.lbeg", + .translate = translate_xsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "xsr.lcount", + .translate = translate_xsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "xsr.lend", + .translate = translate_xsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "xsr.litbase", + .translate = translate_xsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "xsr.m0", + .translate = translate_xsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "xsr.m1", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "xsr.m2", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "xsr.m3", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "xsr.memctl", + .translate = translate_xsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "xsr.misc0", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "xsr.misc1", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "xsr.misc2", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "xsr.misc3", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "xsr.prid", + .translate = translate_xsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "xsr.ps", + .translate = translate_xsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "xsr.ptevaddr", + .translate = translate_xsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "xsr.rasid", + .translate = translate_xsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "xsr.sar", + .translate = translate_xsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "xsr.scompare1", + .translate = translate_xsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "xsr.vecbase", + .translate = translate_xsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "xsr.windowbase", + .translate = translate_xsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "xsr.windowstart", + .translate = translate_xsr, + .par = (const uint32_t[]){WINDOW_START}, + }, +}; + +const XtensaOpcodeTranslators xtensa_core_opcodes = { + .num_opcodes = ARRAY_SIZE(core_ops), + .opcode = core_ops, +}; + + +static void translate_abs_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_add_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_add_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +enum { + COMPARE_UN, + COMPARE_OEQ, + COMPARE_UEQ, + COMPARE_OLT, + COMPARE_ULT, + COMPARE_OLE, + COMPARE_ULE, +}; + +static void translate_compare_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_env env, TCGv_i32 bit, + TCGv_i32 s, TCGv_i32 t) = { + [COMPARE_UN] = gen_helper_un_s, + [COMPARE_OEQ] = gen_helper_oeq_s, + [COMPARE_UEQ] = gen_helper_ueq_s, + [COMPARE_OLT] = gen_helper_olt_s, + [COMPARE_ULT] = gen_helper_ult_s, + [COMPARE_OLE] = gen_helper_ole_s, + [COMPARE_ULE] = gen_helper_ule_s, + }; + + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 bit = tcg_const_i32(1 << arg[0]); + + helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(bit); + } +} + +static void translate_float_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 scale = tcg_const_i32(-arg[2]); + + if (par[0]) { + gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } else { + gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } + tcg_temp_free(scale); + } +} + +static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 rounding_mode = tcg_const_i32(par[0]); + TCGv_i32 scale = tcg_const_i32(arg[2]); + + if (par[1]) { + gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } +} + +static void translate_ldsti(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_ldstx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_madd_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_mov_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], + cpu_R[arg[2]], zero, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(zero); + } +} + +static void translate_movp_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_FR[arg[0]], tmp, zero, + cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } +} + +static void translate_mul_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_msub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_neg_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_sub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); + } +} + +static const XtensaOpcodeOps fpu2000_ops[] = { + { + .name = "abs.s", + .translate = translate_abs_s, + }, { + .name = "add.s", + .translate = translate_add_s, + }, { + .name = "ceil.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_up, false}, + }, { + .name = "float.s", + .translate = translate_float_s, + .par = (const uint32_t[]){false}, + }, { + .name = "floor.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_down, false}, + }, { + .name = "lsi", + .translate = translate_ldsti, + .par = (const uint32_t[]){false, false}, + }, { + .name = "lsiu", + .translate = translate_ldsti, + .par = (const uint32_t[]){false, true}, + }, { + .name = "lsx", + .translate = translate_ldstx, + .par = (const uint32_t[]){false, false}, + }, { + .name = "lsxu", + .translate = translate_ldstx, + .par = (const uint32_t[]){false, true}, + }, { + .name = "madd.s", + .translate = translate_madd_s, + }, { + .name = "mov.s", + .translate = translate_mov_s, + }, { + .name = "moveqz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movf.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movgez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "movltz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "movnez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "movt.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "msub.s", + .translate = translate_msub_s, + }, { + .name = "mul.s", + .translate = translate_mul_s, + }, { + .name = "neg.s", + .translate = translate_neg_s, + }, { + .name = "oeq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OEQ}, + }, { + .name = "ole.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLE}, + }, { + .name = "olt.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLT}, + }, { + .name = "rfr.s", + .translate = translate_rfr_s, + }, { + .name = "round.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_nearest_even, false}, + }, { + .name = "ssi", + .translate = translate_ldsti, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ssiu", + .translate = translate_ldsti, + .par = (const uint32_t[]){true, true}, + }, { + .name = "ssx", + .translate = translate_ldstx, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ssxu", + .translate = translate_ldstx, + .par = (const uint32_t[]){true, true}, + }, { + .name = "sub.s", + .translate = translate_sub_s, + }, { + .name = "trunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, false}, + }, { + .name = "ueq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UEQ}, + }, { + .name = "ufloat.s", + .translate = translate_float_s, + .par = (const uint32_t[]){true}, + }, { + .name = "ule.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULE}, + }, { + .name = "ult.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULT}, + }, { + .name = "un.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UN}, + }, { + .name = "utrunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, true}, + }, { + .name = "wfr.s", + .translate = translate_wfr_s, + }, +}; + +const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { + .num_opcodes = ARRAY_SIZE(fpu2000_ops), + .opcode = fpu2000_ops, +}; diff --git a/target/xtensa/xtensa-isa-internal.h b/target/xtensa/xtensa-isa-internal.h new file mode 100644 index 0000000..c29295f --- /dev/null +++ b/target/xtensa/xtensa-isa-internal.h @@ -0,0 +1,231 @@ +/* Internal definitions for the Xtensa ISA library. + * + * Copyright (c) 2004-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_ISA_INTERNAL_H +#define XTENSA_ISA_INTERNAL_H + +#ifndef uint32 +#define uint32 uint32_t +#endif + +/* Flags. */ + +#define XTENSA_OPERAND_IS_REGISTER 0x00000001 +#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002 +#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004 +#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008 + +#define XTENSA_OPCODE_IS_BRANCH 0x00000001 +#define XTENSA_OPCODE_IS_JUMP 0x00000002 +#define XTENSA_OPCODE_IS_LOOP 0x00000004 +#define XTENSA_OPCODE_IS_CALL 0x00000008 + +#define XTENSA_STATE_IS_EXPORTED 0x00000001 +#define XTENSA_STATE_IS_SHARED_OR 0x00000002 + +#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001 + +/* Function pointer typedefs */ +typedef void (*xtensa_format_encode_fn)(xtensa_insnbuf); +typedef void (*xtensa_get_slot_fn)(const xtensa_insnbuf, xtensa_insnbuf); +typedef void (*xtensa_set_slot_fn)(xtensa_insnbuf, const xtensa_insnbuf); +typedef int (*xtensa_opcode_decode_fn)(const xtensa_insnbuf); +typedef uint32_t (*xtensa_get_field_fn)(const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn)(xtensa_insnbuf, uint32_t); +typedef int (*xtensa_immed_decode_fn)(uint32_t *); +typedef int (*xtensa_immed_encode_fn)(uint32_t *); +typedef int (*xtensa_do_reloc_fn)(uint32_t *, uint32_t); +typedef int (*xtensa_undo_reloc_fn)(uint32_t *, uint32_t); +typedef void (*xtensa_opcode_encode_fn)(xtensa_insnbuf); +typedef int (*xtensa_format_decode_fn)(const xtensa_insnbuf); +typedef int (*xtensa_length_decode_fn)(const unsigned char *); + +typedef struct xtensa_format_internal_struct { + const char *name; /* Instruction format name. */ + int length; /* Instruction length in bytes. */ + xtensa_format_encode_fn encode_fn; + int num_slots; + int *slot_id; /* Array[num_slots] of slot IDs. */ +} xtensa_format_internal; + +typedef struct xtensa_slot_internal_struct { + const char *name; /* Not necessarily unique. */ + const char *format; + int position; + xtensa_get_slot_fn get_fn; + xtensa_set_slot_fn set_fn; + xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */ + xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */ + xtensa_opcode_decode_fn opcode_decode_fn; + const char *nop_name; +} xtensa_slot_internal; + +typedef struct xtensa_operand_internal_struct { + const char *name; + int field_id; + xtensa_regfile regfile; /* Register file. */ + int num_regs; /* Usually 1; 2 for reg pairs, etc. */ + uint32_t flags; /* See XTENSA_OPERAND_* flags. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + +typedef struct xtensa_arg_internal_struct { + union { + int operand_id; /* For normal operands. */ + xtensa_state state; /* For stateOperands. */ + } u; + char inout; /* Direction: 'i', 'o', or 'm'. */ +} xtensa_arg_internal; + +typedef struct xtensa_iclass_internal_struct { + int num_operands; /* Size of "operands" array. */ + xtensa_arg_internal *operands; /* Array[num_operands]. */ + + int num_stateOperands; /* Size of "stateOperands" array. */ + xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */ + + int num_interfaceOperands; /* Size of "interfaceOperands". */ + xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */ +} xtensa_iclass_internal; + +typedef struct xtensa_opcode_internal_struct { + const char *name; /* Opcode mnemonic. */ + int iclass_id; /* Iclass for this opcode. */ + uint32_t flags; /* See XTENSA_OPCODE_* flags. */ + xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */ + int num_funcUnit_uses; /* Number of funcUnit_use entries. */ + xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */ +} xtensa_opcode_internal; + +typedef struct xtensa_regfile_internal_struct { + const char *name; /* Full name of the regfile. */ + const char *shortname; /* Abbreviated name. */ + xtensa_regfile parent; /* View parent (or identity). */ + int num_bits; /* Width of the registers. */ + int num_entries; /* Number of registers. */ +} xtensa_regfile_internal; + +typedef struct xtensa_interface_internal_struct { + const char *name; /* Interface name. */ + int num_bits; /* Width of the interface. */ + uint32_t flags; /* See XTENSA_INTERFACE_* flags. */ + int class_id; /* Class of related interfaces. */ + char inout; /* "i" or "o". */ +} xtensa_interface_internal; + +typedef struct xtensa_funcUnit_internal_struct { + const char *name; /* Functional unit name. */ + int num_copies; /* Number of instances. */ +} xtensa_funcUnit_internal; + +typedef struct xtensa_state_internal_struct { + const char *name; /* State name. */ + int num_bits; /* Number of state bits. */ + uint32_t flags; /* See XTENSA_STATE_* flags. */ +} xtensa_state_internal; + +typedef struct xtensa_sysreg_internal_struct { + const char *name; /* Register name. */ + int number; /* Register number. */ + int is_user; /* Non-zero if a "user register". */ +} xtensa_sysreg_internal; + +typedef struct xtensa_lookup_entry_struct { + const char *key; + union { + xtensa_opcode opcode; /* Internal opcode number. */ + xtensa_sysreg sysreg; /* Internal sysreg number. */ + xtensa_state state; /* Internal state number. */ + xtensa_interface intf; /* Internal interface number. */ + xtensa_funcUnit fun; /* Internal funcUnit number. */ + } u; +} xtensa_lookup_entry; + +typedef struct xtensa_isa_internal_struct { + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + + int num_formats; + xtensa_format_internal *formats; + xtensa_format_decode_fn format_decode_fn; + xtensa_length_decode_fn length_decode_fn; + + int num_slots; + xtensa_slot_internal *slots; + + int num_fields; + + int num_operands; + xtensa_operand_internal *operands; + + int num_iclasses; + xtensa_iclass_internal *iclasses; + + int num_opcodes; + xtensa_opcode_internal *opcodes; + xtensa_lookup_entry *opname_lookup_table; + + int num_regfiles; + xtensa_regfile_internal *regfiles; + + int num_states; + xtensa_state_internal *states; + xtensa_lookup_entry *state_lookup_table; + + int num_sysregs; + xtensa_sysreg_internal *sysregs; + xtensa_lookup_entry *sysreg_lookup_table; + + /* + * The current Xtensa ISA only supports 256 of each kind of sysreg so + * we can get away with implementing lookups with tables indexed by + * the register numbers. If we ever allow larger sysreg numbers, this + * may have to be reimplemented. The first entry in the following + * arrays corresponds to "special" registers and the second to "user" + * registers. + */ + int max_sysreg_num[2]; + xtensa_sysreg *sysreg_table[2]; + + int num_interfaces; + xtensa_interface_internal *interfaces; + xtensa_lookup_entry *interface_lookup_table; + + int num_funcUnits; + xtensa_funcUnit_internal *funcUnits; + xtensa_lookup_entry *funcUnit_lookup_table; + + int num_stages; /* Number of pipe stages. */ +} xtensa_isa_internal; + +int xtensa_isa_name_compare(const void *, const void *); + +extern xtensa_isa_status xtisa_errno; +extern char xtisa_error_msg[]; + +#endif /* !XTENSA_ISA_INTERNAL_H */ diff --git a/target/xtensa/xtensa-isa.c b/target/xtensa/xtensa-isa.c new file mode 100644 index 0000000..e0076a6 --- /dev/null +++ b/target/xtensa/xtensa-isa.c @@ -0,0 +1,1745 @@ +/* Configurable Xtensa ISA support. + * + * Copyright (c) 2001-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + +xtensa_isa_status xtisa_errno; +char xtisa_error_msg[1024]; + + +xtensa_isa_status xtensa_isa_errno(xtensa_isa isa __attribute__ ((unused))) +{ + return xtisa_errno; +} + + +char *xtensa_isa_error_msg(xtensa_isa isa __attribute__ ((unused))) +{ + return xtisa_error_msg; +} + + +#define CHECK_ALLOC(MEM, ERRVAL) \ + do { \ + if ((MEM) == 0) { \ + xtisa_errno = xtensa_isa_out_of_memory; \ + strcpy(xtisa_error_msg, "out of memory"); \ + return ERRVAL; \ + } \ + } while (0) + +#define CHECK_ALLOC_FOR_INIT(MEM, ERRVAL, ERRNO_P, ERROR_MSG_P) \ + do { \ + if ((MEM) == 0) { \ + xtisa_errno = xtensa_isa_out_of_memory; \ + strcpy(xtisa_error_msg, "out of memory"); \ + if (ERRNO_P) { \ + *(ERRNO_P) = xtisa_errno; \ + } \ + if (ERROR_MSG_P) { \ + *(ERROR_MSG_P) = xtisa_error_msg; \ + } \ + return ERRVAL; \ + } \ + } while (0) + + +/* Instruction buffers. */ + +int xtensa_insnbuf_size(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->insnbuf_size; +} + + +xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa) +{ + xtensa_insnbuf result = (xtensa_insnbuf) + malloc(xtensa_insnbuf_size(isa) * sizeof(xtensa_insnbuf_word)); + + CHECK_ALLOC(result, 0); + return result; +} + + +void xtensa_insnbuf_free(xtensa_isa isa __attribute__ ((unused)), + xtensa_insnbuf buf) +{ + free(buf); +} + + +/* + * Given <byte_index>, the index of a byte in a xtensa_insnbuf, our + * internal representation of a xtensa instruction word, return the index of + * its word and the bit index of its low order byte in the xtensa_insnbuf. + */ + +static inline int byte_to_word_index(int byte_index) +{ + return byte_index / sizeof(xtensa_insnbuf_word); +} + + +static inline int byte_to_bit_index(int byte_index) +{ + return (byte_index & 0x3) * 8; +} + + +/* + * Copy an instruction in the 32-bit words pointed at by "insn" to + * characters pointed at by "cp". This is more complicated than you + * might think because we want 16-bit instructions in bytes 2 & 3 for + * big-endian configurations. This function allows us to specify + * which byte in "insn" to start with and which way to increment, + * allowing trivial implementation for both big- and little-endian + * configurations....and it seems to make pretty good code for + * both. + */ + +int xtensa_insnbuf_to_chars(xtensa_isa isa, + const xtensa_insnbuf insn, + unsigned char *cp, + int num_chars) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int insn_size = xtensa_isa_maxlength(isa); + int fence_post, start, increment, i, byte_count; + xtensa_format fmt; + + if (num_chars == 0) { + num_chars = insn_size; + } + + if (intisa->is_big_endian) { + start = insn_size - 1; + increment = -1; + } else { + start = 0; + increment = 1; + } + + /* + * Find the instruction format. Do nothing if the buffer does not contain + * a valid instruction since we need to know how many bytes to copy. + */ + fmt = xtensa_format_decode(isa, insn); + if (fmt == XTENSA_UNDEFINED) { + return XTENSA_UNDEFINED; + } + + byte_count = xtensa_format_length(isa, fmt); + if (byte_count == XTENSA_UNDEFINED) { + return XTENSA_UNDEFINED; + } + + if (byte_count > num_chars) { + xtisa_errno = xtensa_isa_buffer_overflow; + strcpy(xtisa_error_msg, "output buffer too small for instruction"); + return XTENSA_UNDEFINED; + } + + fence_post = start + (byte_count * increment); + + for (i = start; i != fence_post; i += increment, ++cp) { + int word_inx = byte_to_word_index(i); + int bit_inx = byte_to_bit_index(i); + + *cp = (insn[word_inx] >> bit_inx) & 0xff; + } + + return byte_count; +} + + +/* + * Inward conversion from byte stream to xtensa_insnbuf. See + * xtensa_insnbuf_to_chars for a discussion of why this is complicated + * by endianness. + */ + +void xtensa_insnbuf_from_chars(xtensa_isa isa, + xtensa_insnbuf insn, + const unsigned char *cp, + int num_chars) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int max_size, insn_size, fence_post, start, increment, i; + + max_size = xtensa_isa_maxlength(isa); + + /* Decode the instruction length so we know how many bytes to read. */ + insn_size = (intisa->length_decode_fn)(cp); + if (insn_size == XTENSA_UNDEFINED) { + /* + * This should never happen when the byte stream contains a + * valid instruction. Just read the maximum number of bytes.... + */ + insn_size = max_size; + } + + if (num_chars == 0 || num_chars > insn_size) { + num_chars = insn_size; + } + + if (intisa->is_big_endian) { + start = max_size - 1; + increment = -1; + } else { + start = 0; + increment = 1; + } + + fence_post = start + (num_chars * increment); + memset(insn, 0, xtensa_insnbuf_size(isa) * sizeof(xtensa_insnbuf_word)); + + for (i = start; i != fence_post; i += increment, ++cp) { + int word_inx = byte_to_word_index(i); + int bit_inx = byte_to_bit_index(i); + + insn[word_inx] |= (*cp & 0xff) << bit_inx; + } +} + + +/* ISA information. */ + +xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p, + char **error_msg_p) +{ + xtensa_isa_internal *isa = xtensa_modules; + int n, is_user; + + /* Set up the opcode name lookup table. */ + isa->opname_lookup_table = + malloc(isa->num_opcodes * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->opname_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_opcodes; n++) { + isa->opname_lookup_table[n].key = isa->opcodes[n].name; + isa->opname_lookup_table[n].u.opcode = n; + } + qsort(isa->opname_lookup_table, isa->num_opcodes, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the state name lookup table. */ + isa->state_lookup_table = + malloc(isa->num_states * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->state_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_states; n++) { + isa->state_lookup_table[n].key = isa->states[n].name; + isa->state_lookup_table[n].u.state = n; + } + qsort(isa->state_lookup_table, isa->num_states, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the sysreg name lookup table. */ + isa->sysreg_lookup_table = + malloc(isa->num_sysregs * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->sysreg_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_sysregs; n++) { + isa->sysreg_lookup_table[n].key = isa->sysregs[n].name; + isa->sysreg_lookup_table[n].u.sysreg = n; + } + qsort(isa->sysreg_lookup_table, isa->num_sysregs, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the user & system sysreg number tables. */ + for (is_user = 0; is_user < 2; is_user++) { + isa->sysreg_table[is_user] = + malloc((isa->max_sysreg_num[is_user] + 1) * sizeof(xtensa_sysreg)); + CHECK_ALLOC_FOR_INIT(isa->sysreg_table[is_user], NULL, + errno_p, error_msg_p); + + for (n = 0; n <= isa->max_sysreg_num[is_user]; n++) { + isa->sysreg_table[is_user][n] = XTENSA_UNDEFINED; + } + } + for (n = 0; n < isa->num_sysregs; n++) { + xtensa_sysreg_internal *sreg = &isa->sysregs[n]; + is_user = sreg->is_user; + + if (sreg->number >= 0) { + isa->sysreg_table[is_user][sreg->number] = n; + } + } + + /* Set up the interface lookup table. */ + isa->interface_lookup_table = + malloc(isa->num_interfaces * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->interface_lookup_table, NULL, errno_p, + error_msg_p); + for (n = 0; n < isa->num_interfaces; n++) { + isa->interface_lookup_table[n].key = isa->interfaces[n].name; + isa->interface_lookup_table[n].u.intf = n; + } + qsort(isa->interface_lookup_table, isa->num_interfaces, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the funcUnit lookup table. */ + isa->funcUnit_lookup_table = + malloc(isa->num_funcUnits * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->funcUnit_lookup_table, NULL, errno_p, + error_msg_p); + for (n = 0; n < isa->num_funcUnits; n++) { + isa->funcUnit_lookup_table[n].key = isa->funcUnits[n].name; + isa->funcUnit_lookup_table[n].u.fun = n; + } + qsort(isa->funcUnit_lookup_table, isa->num_funcUnits, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + isa->insnbuf_size = ((isa->insn_size + sizeof(xtensa_insnbuf_word) - 1) / + sizeof(xtensa_insnbuf_word)); + isa->num_stages = XTENSA_UNDEFINED; + + return (xtensa_isa)isa; +} + + +void xtensa_isa_free(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + /* + * With this version of the code, the xtensa_isa structure is not + * dynamically allocated, so this function is not essential. Free + * the memory allocated by xtensa_isa_init and restore the xtensa_isa + * structure to its initial state. + */ + + if (intisa->opname_lookup_table) { + free(intisa->opname_lookup_table); + intisa->opname_lookup_table = 0; + } + + if (intisa->state_lookup_table) { + free(intisa->state_lookup_table); + intisa->state_lookup_table = 0; + } + + if (intisa->sysreg_lookup_table) { + free(intisa->sysreg_lookup_table); + intisa->sysreg_lookup_table = 0; + } + for (n = 0; n < 2; n++) { + if (intisa->sysreg_table[n]) { + free(intisa->sysreg_table[n]); + intisa->sysreg_table[n] = 0; + } + } + + if (intisa->interface_lookup_table) { + free(intisa->interface_lookup_table); + intisa->interface_lookup_table = 0; + } + + if (intisa->funcUnit_lookup_table) { + free(intisa->funcUnit_lookup_table); + intisa->funcUnit_lookup_table = 0; + } +} + + +int xtensa_isa_name_compare(const void *v1, const void *v2) +{ + xtensa_lookup_entry *e1 = (xtensa_lookup_entry *)v1; + xtensa_lookup_entry *e2 = (xtensa_lookup_entry *)v2; + + return strcasecmp(e1->key, e2->key); +} + + +int xtensa_isa_maxlength(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->insn_size; +} + + +int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return (intisa->length_decode_fn)(cp); +} + + +int xtensa_isa_num_pipe_stages(xtensa_isa isa) +{ + xtensa_opcode opcode; + xtensa_funcUnit_use *use; + int num_opcodes, num_uses; + int i, stage, max_stage; + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + /* Only compute the value once. */ + if (intisa->num_stages != XTENSA_UNDEFINED) { + return intisa->num_stages; + } + + max_stage = -1; + + num_opcodes = xtensa_isa_num_opcodes(isa); + for (opcode = 0; opcode < num_opcodes; opcode++) { + num_uses = xtensa_opcode_num_funcUnit_uses(isa, opcode); + for (i = 0; i < num_uses; i++) { + use = xtensa_opcode_funcUnit_use(isa, opcode, i); + stage = use->stage; + if (stage > max_stage) { + max_stage = stage; + } + } + } + + intisa->num_stages = max_stage + 1; + return intisa->num_states; +} + + +int xtensa_isa_num_formats(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_formats; +} + + +int xtensa_isa_num_opcodes(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_opcodes; +} + + +int xtensa_isa_num_regfiles(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_regfiles; +} + + +int xtensa_isa_num_states(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_states; +} + + +int xtensa_isa_num_sysregs(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_sysregs; +} + + +int xtensa_isa_num_interfaces(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_interfaces; +} + + +int xtensa_isa_num_funcUnits(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_funcUnits; +} + + +/* Instruction formats. */ + + +#define CHECK_FORMAT(INTISA, FMT, ERRVAL) \ + do { \ + if ((FMT) < 0 || (FMT) >= (INTISA)->num_formats) { \ + xtisa_errno = xtensa_isa_bad_format; \ + strcpy(xtisa_error_msg, "invalid format specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +#define CHECK_SLOT(INTISA, FMT, SLOT, ERRVAL) \ + do { \ + if ((SLOT) < 0 || (SLOT) >= (INTISA)->formats[FMT].num_slots) { \ + xtisa_errno = xtensa_isa_bad_slot; \ + strcpy(xtisa_error_msg, "invalid slot specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, NULL); + return intisa->formats[fmt].name; +} + + +xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int fmt; + + if (!fmtname || !*fmtname) { + xtisa_errno = xtensa_isa_bad_format; + strcpy(xtisa_error_msg, "invalid format name"); + return XTENSA_UNDEFINED; + } + + for (fmt = 0; fmt < intisa->num_formats; fmt++) { + if (strcasecmp(fmtname, intisa->formats[fmt].name) == 0) { + return fmt; + } + } + + xtisa_errno = xtensa_isa_bad_format; + sprintf(xtisa_error_msg, "format \"%s\" not recognized", fmtname); + return XTENSA_UNDEFINED; +} + + +xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_format fmt; + + fmt = (intisa->format_decode_fn)(insn); + if (fmt != XTENSA_UNDEFINED) { + return fmt; + } + + xtisa_errno = xtensa_isa_bad_format; + strcpy(xtisa_error_msg, "cannot decode instruction format"); + return XTENSA_UNDEFINED; +} + + +int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt, + xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, -1); + (*intisa->formats[fmt].encode_fn)(insn); + return 0; +} + + +int xtensa_format_length(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + return intisa->formats[fmt].length; +} + + +int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + return intisa->formats[fmt].num_slots; +} + + +xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt, + int slot) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + CHECK_SLOT(intisa, fmt, slot, XTENSA_UNDEFINED); + + slot_id = intisa->formats[fmt].slot_id[slot]; + return xtensa_opcode_lookup(isa, intisa->slots[slot_id].nop_name); +} + + +int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + (*intisa->slots[slot_id].get_fn)(insn, slotbuf); + return 0; +} + + +int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + (*intisa->slots[slot_id].set_fn)(insn, slotbuf); + return 0; +} + + +/* Opcode information. */ + + +#define CHECK_OPCODE(INTISA, OPC, ERRVAL) \ + do { \ + if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) { \ + xtisa_errno = xtensa_isa_bad_opcode; \ + strcpy(xtisa_error_msg, "invalid opcode specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!opname || !*opname) { + xtisa_errno = xtensa_isa_bad_opcode; + strcpy(xtisa_error_msg, "invalid opcode name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_opcodes != 0) { + entry.key = opname; + result = bsearch(&entry, intisa->opname_lookup_table, + intisa->num_opcodes, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_opcode; + sprintf(xtisa_error_msg, "opcode \"%s\" not recognized", opname); + return XTENSA_UNDEFINED; + } + + return result->u.opcode; +} + + +xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + xtensa_opcode opc; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + CHECK_SLOT(intisa, fmt, slot, XTENSA_UNDEFINED); + + slot_id = intisa->formats[fmt].slot_id[slot]; + + opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); + if (opc != XTENSA_UNDEFINED) { + return opc; + } + + xtisa_errno = xtensa_isa_bad_opcode; + strcpy(xtisa_error_msg, "cannot decode opcode"); + return XTENSA_UNDEFINED; +} + + +int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + xtensa_opcode_encode_fn encode_fn; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + CHECK_OPCODE(intisa, opc, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; + if (!encode_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "opcode \"%s\" is not allowed in slot %d of format \"%s\"", + intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); + return -1; + } + (*encode_fn)(slotbuf); + return 0; +} + + +const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, NULL); + return intisa->opcodes[opc].name; +} + + +int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_BRANCH) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_JUMP) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_LOOP) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_CALL) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_operands; +} + + +int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_stateOperands; +} + + +int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_interfaceOperands; +} + + +int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + return intisa->opcodes[opc].num_funcUnit_uses; +} + + +xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa, + xtensa_opcode opc, int u) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, NULL); + if (u < 0 || u >= intisa->opcodes[opc].num_funcUnit_uses) { + xtisa_errno = xtensa_isa_bad_funcUnit; + sprintf(xtisa_error_msg, "invalid functional unit use number (%d); " + "opcode \"%s\" has %d", u, intisa->opcodes[opc].name, + intisa->opcodes[opc].num_funcUnit_uses); + return NULL; + } + return &intisa->opcodes[opc].funcUnit_uses[u]; +} + + +/* Operand information. */ + + +#define CHECK_OPERAND(INTISA, OPC, ICLASS, OPND, ERRVAL) \ + do { \ + if ((OPND) < 0 || (OPND) >= (ICLASS)->num_operands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, "invalid operand number (%d); " \ + "opcode \"%s\" has %d operands", (OPND), \ + (INTISA)->opcodes[(OPC)].name, (ICLASS)->num_operands); \ + return ERRVAL; \ + } \ + } while (0) + + +static xtensa_operand_internal *get_operand(xtensa_isa_internal *intisa, + xtensa_opcode opc, int opnd) +{ + xtensa_iclass_internal *iclass; + int iclass_id, operand_id; + + CHECK_OPCODE(intisa, opc, NULL); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, NULL); + operand_id = iclass->operands[opnd].u.operand_id; + return &intisa->operands[operand_id]; +} + + +const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return NULL; + } + return intop->name; +} + + +int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id, operand_id; + xtensa_operand_internal *intop; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, XTENSA_UNDEFINED); + + /* Special case for "sout" operands. */ + if (iclass->operands[opnd].inout == 's') { + return 0; + } + + operand_id = iclass->operands[opnd].u.operand_id; + intop = &intisa->operands[operand_id]; + + if ((intop->flags & XTENSA_OPERAND_IS_INVISIBLE) == 0) { + return 1; + } + return 0; +} + + +char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + char inout; + + CHECK_OPCODE(intisa, opc, 0); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, 0); + inout = iclass->operands[opnd].inout; + + /* Special case for "sout" and "_sin" operands. */ + if (inout == 's') { + return 'o'; + } + if (inout == 't') { + return 'i'; + } + return inout; +} + + +int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + int slot_id; + xtensa_get_field_fn get_fn; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "implicit operand has no field"); + return -1; + } + get_fn = intisa->slots[slot_id].get_field_fns[intop->field_id]; + if (!get_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "operand \"%s\" does not exist in slot %d of format \"%s\"", + intop->name, slot, intisa->formats[fmt].name); + return -1; + } + *valp = (*get_fn)(slotbuf); + return 0; +} + + +int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32_t val) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + int slot_id; + xtensa_set_field_fn set_fn; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "implicit operand has no field"); + return -1; + } + set_fn = intisa->slots[slot_id].set_field_fns[intop->field_id]; + if (!set_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "operand \"%s\" does not exist in slot %d of format \"%s\"", + intop->name, slot, intisa->formats[fmt].name); + return -1; + } + (*set_fn)(slotbuf, val); + return 0; +} + + +int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + uint32_t test_val, orig_val; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if (!intop->encode) { + /* + * This is a default operand for a field. How can we tell if the + * value fits in the field? Write the value into the field, + * read it back, and then make sure we get the same value. + */ + static xtensa_insnbuf tmpbuf; + int slot_id; + + if (!tmpbuf) { + tmpbuf = xtensa_insnbuf_alloc(isa); + CHECK_ALLOC(tmpbuf, -1); + } + + /* + * A default operand is always associated with a field, + * but check just to be sure.... + */ + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand has no field"); + return -1; + } + + /* Find some slot that includes the field. */ + for (slot_id = 0; slot_id < intisa->num_slots; slot_id++) { + xtensa_get_field_fn get_fn = + intisa->slots[slot_id].get_field_fns[intop->field_id]; + xtensa_set_field_fn set_fn = + intisa->slots[slot_id].set_field_fns[intop->field_id]; + + if (get_fn && set_fn) { + (*set_fn)(tmpbuf, *valp); + return (*get_fn)(tmpbuf) != *valp; + } + } + + /* Couldn't find any slot containing the field.... */ + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "field does not exist in any slot"); + return -1; + } + + /* + * Encode the value. In some cases, the encoding function may detect + * errors, but most of the time the only way to determine if the value + * was successfully encoded is to decode it and check if it matches + * the original value. + */ + orig_val = *valp; + if ((*intop->encode)(valp) || + (test_val = *valp, (*intop->decode)(&test_val)) || + test_val != orig_val) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, "cannot encode operand value 0x%08x", *valp); + return -1; + } + + return 0; +} + + +int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + /* Use identity function for "default" operands. */ + if (!intop->decode) { + return 0; + } + + if ((*intop->decode)(valp)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, "cannot decode operand value 0x%08x", *valp); + return -1; + } + return 0; +} + + +int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_REGISTER) != 0) { + return 1; + } + return 0; +} + + +xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc, + int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + return intop->regfile; +} + + +int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + return intop->num_regs; +} + + +int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_UNKNOWN) == 0) { + return 1; + } + return 0; +} + + +int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) != 0) { + return 1; + } + return 0; +} + + +int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) { + return 0; + } + + if (!intop->do_reloc) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand missing do_reloc function"); + return -1; + } + + if ((*intop->do_reloc)(valp, pc)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, + "do_reloc failed for value 0x%08x at PC 0x%08x", *valp, pc); + return -1; + } + + return 0; +} + + +int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) { + return 0; + } + + if (!intop->undo_reloc) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand missing undo_reloc function"); + return -1; + } + + if ((*intop->undo_reloc)(valp, pc)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, + "undo_reloc failed for value 0x%08x at PC 0x%08x", *valp, pc); + return -1; + } + + return 0; +} + + +/* State Operands. */ + + +#define CHECK_STATE_OPERAND(INTISA, OPC, ICLASS, STOP, ERRVAL) \ + do { \ + if ((STOP) < 0 || (STOP) >= (ICLASS)->num_stateOperands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, "invalid state operand number (%d); " \ + "opcode \"%s\" has %d state operands", (STOP), \ + (INTISA)->opcodes[(OPC)].name, \ + (ICLASS)->num_stateOperands); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc, + int stOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_STATE_OPERAND(intisa, opc, iclass, stOp, XTENSA_UNDEFINED); + return iclass->stateOperands[stOp].u.state; +} + + +char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, 0); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_STATE_OPERAND(intisa, opc, iclass, stOp, 0); + return iclass->stateOperands[stOp].inout; +} + + +/* Interface Operands. */ + + +#define CHECK_INTERFACE_OPERAND(INTISA, OPC, ICLASS, IFOP, ERRVAL) \ + do { \ + if ((IFOP) < 0 || (IFOP) >= (ICLASS)->num_interfaceOperands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, \ + "invalid interface operand number (%d); " \ + "opcode \"%s\" has %d interface operands", (IFOP), \ + (INTISA)->opcodes[(OPC)].name, \ + (ICLASS)->num_interfaceOperands); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa, + xtensa_opcode opc, + int ifOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_INTERFACE_OPERAND(intisa, opc, iclass, ifOp, XTENSA_UNDEFINED); + return iclass->interfaceOperands[ifOp]; +} + + +/* Register Files. */ + + +#define CHECK_REGFILE(INTISA, RF, ERRVAL) \ + do { \ + if ((RF) < 0 || (RF) >= (INTISA)->num_regfiles) { \ + xtisa_errno = xtensa_isa_bad_regfile; \ + strcpy(xtisa_error_msg, "invalid regfile specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_regfile; + strcpy(xtisa_error_msg, "invalid regfile name"); + return XTENSA_UNDEFINED; + } + + /* The expected number of regfiles is small; use a linear search. */ + for (n = 0; n < intisa->num_regfiles; n++) { + if (!strcmp(intisa->regfiles[n].name, name)) { + return n; + } + } + + xtisa_errno = xtensa_isa_bad_regfile; + sprintf(xtisa_error_msg, "regfile \"%s\" not recognized", name); + return XTENSA_UNDEFINED; +} + + +xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa, + const char *shortname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + if (!shortname || !*shortname) { + xtisa_errno = xtensa_isa_bad_regfile; + strcpy(xtisa_error_msg, "invalid regfile shortname"); + return XTENSA_UNDEFINED; + } + + /* The expected number of regfiles is small; use a linear search. */ + for (n = 0; n < intisa->num_regfiles; n++) { + /* + * Ignore regfile views since they always have the same shortnames + * as their parents. + */ + if (intisa->regfiles[n].parent != n) { + continue; + } + if (!strcmp(intisa->regfiles[n].shortname, shortname)) { + return n; + } + } + + xtisa_errno = xtensa_isa_bad_regfile; + sprintf(xtisa_error_msg, "regfile shortname \"%s\" not recognized", + shortname); + return XTENSA_UNDEFINED; +} + + +const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, NULL); + return intisa->regfiles[rf].name; +} + + +const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, NULL); + return intisa->regfiles[rf].shortname; +} + + +xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].parent; +} + + +int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].num_bits; +} + + +int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].num_entries; +} + + +/* Processor States. */ + + +#define CHECK_STATE(INTISA, ST, ERRVAL) \ + do { \ + if ((ST) < 0 || (ST) >= (INTISA)->num_states) { \ + xtisa_errno = xtensa_isa_bad_state; \ + strcpy(xtisa_error_msg, "invalid state specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_state; + strcpy(xtisa_error_msg, "invalid state name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_states != 0) { + entry.key = name; + result = bsearch(&entry, intisa->state_lookup_table, + intisa->num_states, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_state; + sprintf(xtisa_error_msg, "state \"%s\" not recognized", name); + return XTENSA_UNDEFINED; + } + + return result->u.state; +} + + +const char *xtensa_state_name(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, NULL); + return intisa->states[st].name; +} + + +int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + return intisa->states[st].num_bits; +} + + +int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + if ((intisa->states[st].flags & XTENSA_STATE_IS_EXPORTED) != 0) { + return 1; + } + return 0; +} + + +int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + if ((intisa->states[st].flags & XTENSA_STATE_IS_SHARED_OR) != 0) { + return 1; + } + return 0; +} + + +/* Sysregs. */ + + +#define CHECK_SYSREG(INTISA, SYSREG, ERRVAL) \ + do { \ + if ((SYSREG) < 0 || (SYSREG) >= (INTISA)->num_sysregs) { \ + xtisa_errno = xtensa_isa_bad_sysreg; \ + strcpy(xtisa_error_msg, "invalid sysreg specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + if (is_user != 0) { + is_user = 1; + } + + if (num < 0 || num > intisa->max_sysreg_num[is_user] || + intisa->sysreg_table[is_user][num] == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_bad_sysreg; + strcpy(xtisa_error_msg, "sysreg not recognized"); + return XTENSA_UNDEFINED; + } + + return intisa->sysreg_table[is_user][num]; +} + + +xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_sysreg; + strcpy(xtisa_error_msg, "invalid sysreg name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_sysregs != 0) { + entry.key = name; + result = bsearch(&entry, intisa->sysreg_lookup_table, + intisa->num_sysregs, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_sysreg; + sprintf(xtisa_error_msg, "sysreg \"%s\" not recognized", name); + return XTENSA_UNDEFINED; + } + + return result->u.sysreg; +} + + +const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, NULL); + return intisa->sysregs[sysreg].name; +} + + +int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); + return intisa->sysregs[sysreg].number; +} + + +int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); + if (intisa->sysregs[sysreg].is_user) { + return 1; + } + return 0; +} + + +/* Interfaces. */ + + +#define CHECK_INTERFACE(INTISA, INTF, ERRVAL) \ + do { \ + if ((INTF) < 0 || (INTF) >= (INTISA)->num_interfaces) { \ + xtisa_errno = xtensa_isa_bad_interface; \ + strcpy(xtisa_error_msg, "invalid interface specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!ifname || !*ifname) { + xtisa_errno = xtensa_isa_bad_interface; + strcpy(xtisa_error_msg, "invalid interface name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_interfaces != 0) { + entry.key = ifname; + result = bsearch(&entry, intisa->interface_lookup_table, + intisa->num_interfaces, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_interface; + sprintf(xtisa_error_msg, "interface \"%s\" not recognized", ifname); + return XTENSA_UNDEFINED; + } + + return result->u.intf; +} + + +const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, NULL); + return intisa->interfaces[intf].name; +} + + +int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + return intisa->interfaces[intf].num_bits; +} + + +char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, 0); + return intisa->interfaces[intf].inout; +} + + +int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + if ((intisa->interfaces[intf].flags & + XTENSA_INTERFACE_HAS_SIDE_EFFECT) != 0) { + return 1; + } + return 0; +} + + +int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + return intisa->interfaces[intf].class_id; +} + + +/* Functional Units. */ + + +#define CHECK_FUNCUNIT(INTISA, FUN, ERRVAL) \ + do { \ + if ((FUN) < 0 || (FUN) >= (INTISA)->num_funcUnits) { \ + xtisa_errno = xtensa_isa_bad_funcUnit; \ + strcpy(xtisa_error_msg, "invalid functional unit specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!fname || !*fname) { + xtisa_errno = xtensa_isa_bad_funcUnit; + strcpy(xtisa_error_msg, "invalid functional unit name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_funcUnits != 0) { + entry.key = fname; + result = bsearch(&entry, intisa->funcUnit_lookup_table, + intisa->num_funcUnits, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_funcUnit; + sprintf(xtisa_error_msg, + "functional unit \"%s\" not recognized", fname); + return XTENSA_UNDEFINED; + } + + return result->u.fun; +} + + +const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FUNCUNIT(intisa, fun, NULL); + return intisa->funcUnits[fun].name; +} + + +int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FUNCUNIT(intisa, fun, XTENSA_UNDEFINED); + return intisa->funcUnits[fun].num_copies; +} diff --git a/target/xtensa/xtensa-isa.h b/target/xtensa/xtensa-isa.h new file mode 100644 index 0000000..d06614c --- /dev/null +++ b/target/xtensa/xtensa-isa.h @@ -0,0 +1 @@ +#include <hw/xtensa/xtensa-isa.h> diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index 42e3e5e..052f1e0 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -44,7 +44,6 @@ test_end test_sr acchi, 1 test_sr acclo, 1 -test_sr /*memctl*/97, 0 test_sr_mask /*atomctl*/99, 0, 0 test_sr_mask /*br*/4, 0, 0 test_sr_mask /*cacheattr*/98, 0, 0 @@ -76,6 +75,7 @@ test_sr lcount, 1 test_sr lend, 1 test_sr litbase, 1 test_sr m0, 1 +test_sr_mask /*memctl*/97, 0, 0 test_sr misc0, 1 test_sr_mask /*prefctl*/40, 0, 0 test_sr_mask /*prid*/235, 0, 1 |