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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-14 11:46:43 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:00 +0000 |
| commit | 528dc354b6f3aa82d65141cc60bc0e725e6cae98 (patch) | |
| tree | 88291af86625306a9ecca6ff6a5b3ac693222c01 | |
| parent | 33649de62e40df0060a1c514574e4ef25c4e52e1 (diff) | |
| download | qemu-528dc354b6f3aa82d65141cc60bc0e725e6cae98.zip qemu-528dc354b6f3aa82d65141cc60bc0e725e6cae98.tar.gz qemu-528dc354b6f3aa82d65141cc60bc0e725e6cae98.tar.bz2 | |
target/arm: Flush high bits of sve register after AdvSIMD INS
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b83d09d..bd68588 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn, write_vec_element(s, tmp, rd, dst_index, size); tcg_temp_free_i64(tmp); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } @@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) idx = extract32(imm5, 1 + size, 4 - size); write_vec_element(s, cpu_reg(s, rn), rd, idx, size); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } /* |