diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-14 11:46:42 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:00 +0000 |
| commit | 33649de62e40df0060a1c514574e4ef25c4e52e1 (patch) | |
| tree | 2a72c0d4034ff1791740617dd1e33da064a94bce | |
| parent | 263273bc988e677ebadeaf7d0e49f6792a112db5 (diff) | |
| download | qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.zip qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.tar.gz qemu-33649de62e40df0060a1c514574e4ef25c4e52e1.tar.bz2 | |
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 096a854..b83d09d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7054,6 +7054,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } /* |