diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:31:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:31:07 +0000 |
| commit | 3d3d399e76c204c718f3ec6ef48fd0bb303070ab (patch) | |
| tree | 64a3e00f9a51768a9f1d63eadc9f03be53e9950c | |
| parent | 38ea9ade29e1e3208dc0e82708388c0a1d73ebf2 (diff) | |
| download | qemu-3d3d399e76c204c718f3ec6ef48fd0bb303070ab.zip qemu-3d3d399e76c204c718f3ec6ef48fd0bb303070ab.tar.gz qemu-3d3d399e76c204c718f3ec6ef48fd0bb303070ab.tar.bz2 | |
target/riscv: Set default NaN pattern explicitly
Set the default NaN pattern explicitly for riscv.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c..80b0995 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,6 +1022,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY |