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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:55 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-11 15:30:55 +0000 |
| commit | 67c0df045ec11da24bd2f18f81813ed9ff48b4c5 (patch) | |
| tree | b067ed77ecb5f193b528141648b66912218f0ea9 | |
| parent | 9a31b8d0ad86e12920e01bd4c01516be9f75337e (diff) | |
| download | qemu-67c0df045ec11da24bd2f18f81813ed9ff48b4c5.zip qemu-67c0df045ec11da24bd2f18f81813ed9ff48b4c5.tar.gz qemu-67c0df045ec11da24bd2f18f81813ed9ff48b4c5.tar.bz2 | |
target/xtensa: Set FloatInfZeroNaNRule explicitly
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
| -rw-r--r-- | fpu/softfloat-specialize.c.inc | 2 | ||||
| -rw-r--r-- | target/xtensa/cpu.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85..3062d19 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039a..3163b75 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } |