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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-14 11:46:41 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:00 +0000 |
| commit | 263273bc988e677ebadeaf7d0e49f6792a112db5 (patch) | |
| tree | 8bcf88b6395690d81f0295043897fc57c34b00e9 | |
| parent | 78cedfabd53b6f64e7e64fc84878d848e5df1d08 (diff) | |
| download | qemu-263273bc988e677ebadeaf7d0e49f6792a112db5.zip qemu-263273bc988e677ebadeaf7d0e49f6792a112db5.tar.gz qemu-263273bc988e677ebadeaf7d0e49f6792a112db5.tar.bz2 | |
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 620a429..096a854 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } /* ZIP/UZP/TRN |