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| author | gsomlo <gsomlo@gmail.com> | 2020-12-15 16:11:40 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-15 13:11:40 -0800 |
| commit | 62bb5daea5ef014616b00a63c106afdd07e68ffd (patch) | |
| tree | 66d1d74fd95fa1a6b319ba857d6c3ca4ec434aa5 /machine/machine.mk.in | |
| parent | 5c159feca11473822906ec9595f7593aba60222f (diff) | |
| download | pk-62bb5daea5ef014616b00a63c106afdd07e68ffd.zip pk-62bb5daea5ef014616b00a63c106afdd07e68ffd.tar.gz pk-62bb5daea5ef014616b00a63c106afdd07e68ffd.tar.bz2 | |
Add support for the UART interface on the LiteX SoC (#230)
Tested using the RocketChip CPU option.
(see https://github.com/enjoy-digital/litex)
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Diffstat (limited to 'machine/machine.mk.in')
| -rw-r--r-- | machine/machine.mk.in | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/machine/machine.mk.in b/machine/machine.mk.in index ee0fc36..3543106 100644 --- a/machine/machine.mk.in +++ b/machine/machine.mk.in @@ -15,6 +15,7 @@ machine_hdrs = \ mtrap.h \ uart.h \ uart16550.h \ + uart_litex.h \ finisher.h \ unprivileged_memory.h \ vm.h \ @@ -30,6 +31,7 @@ machine_c_srcs = \ fp_ldst.c \ uart.c \ uart16550.c \ + uart_litex.c \ finisher.c \ misaligned_ldst.c \ flush_icache.c \ @@ -43,4 +45,4 @@ mentry.o: custom.dtb custom.dtb: $(CUSTOM_DTS) dtc -O dtb $^ -o $@ -endif
\ No newline at end of file +endif |