From 62bb5daea5ef014616b00a63c106afdd07e68ffd Mon Sep 17 00:00:00 2001 From: gsomlo Date: Tue, 15 Dec 2020 16:11:40 -0500 Subject: Add support for the UART interface on the LiteX SoC (#230) Tested using the RocketChip CPU option. (see https://github.com/enjoy-digital/litex) Signed-off-by: Gabriel Somlo --- machine/machine.mk.in | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'machine/machine.mk.in') diff --git a/machine/machine.mk.in b/machine/machine.mk.in index ee0fc36..3543106 100644 --- a/machine/machine.mk.in +++ b/machine/machine.mk.in @@ -15,6 +15,7 @@ machine_hdrs = \ mtrap.h \ uart.h \ uart16550.h \ + uart_litex.h \ finisher.h \ unprivileged_memory.h \ vm.h \ @@ -30,6 +31,7 @@ machine_c_srcs = \ fp_ldst.c \ uart.c \ uart16550.c \ + uart_litex.c \ finisher.c \ misaligned_ldst.c \ flush_icache.c \ @@ -43,4 +45,4 @@ mentry.o: custom.dtb custom.dtb: $(CUSTOM_DTS) dtc -O dtb $^ -o $@ -endif \ No newline at end of file +endif -- cgit v1.1