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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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2020-12-30[X86] Add x86_amx type for intel AMX.Luo, Yuanke1-0/+1
The x86_amx is used for AMX intrisics. <256 x i32> is bitcast to x86_amx when it is used by AMX intrinsics, and x86_amx is bitcast to <256 x i32> when it is used by load/store instruction. So amx intrinsics only operate on type x86_amx. It can help to separate amx intrinsics from llvm IR instructions (+-*/). Thank Craig for the idea. This patch depend on https://reviews.llvm.org/D87981. Differential Revision: https://reviews.llvm.org/D91927
2020-12-19[TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.Craig Topper1-3/+11
These properties aren't additive. They are closer to ReadOnly and WriteOnly. The default is ReadWrite. ReadMem cancels the write property and WriteMem cancels the read property. Combining them leaves neither. This patch checks that when we process WriteMem, the Mod flag is still set. And for ReadMem we check that the Ref flag set still set. I've updated 2 target intrinsics that were combining these properties. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D93571
2020-12-09[Tablegen] Use llvm::is_contained (NFC)Kazu Hirata1-4/+1
2020-12-06[TableGen] [CodeGenTarget] Cache the target's instruction namespace.Paul C. Anagnostopoulos1-6/+11
Differential Revision: https://reviews.llvm.org/D92722
2020-11-14[TableGen] Add frontend/backend phase timing capability.Paul C. Anagnostopoulos1-2/+0
Describe in the BackEnd Developer's Guide. Instrument a few backends. Remove an old unused timing facility. Add a null backend for timing the parser. Differential Revision: https://reviews.llvm.org/D91388
2020-10-23[WebAssembly] Implementation of (most) table instructionsPaulo Matos1-15/+17
Implementation of instructions table.get, table.set, table.grow, table.size, table.fill, table.copy. Missing instructions are table.init and elem.drop as they deal with element sections which are not yet implemented. Added more tests to tables.s Differential Revision: https://reviews.llvm.org/D89797
2020-10-12[IR][FIX] Intrinsics - don't apply default willreturn if IntrNoReturn is ↵sstefan11-4/+4
specified Summary: Since willreturn will soon be added as default attribute, we can end up with both noreturn and willreturn on the same intrinsic. This was exposed by llvm.wasm.throw which has IntrNoReturn. Reviewers: jdoerfert, arsenm Differential Revision: https://reviews.llvm.org/D88644
2020-10-09[VE] Add new MVT types for NEC SX Aurora VE vectorKazushi (Jam) Marukawa1-0/+6
This patch adds entries for: v64i64 v128i64 v256i64 v64f64 v128f64 v256f64 Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D88776
2020-09-21[PowerPC] Add vector pair load/store instructions and vector pair register classBaptiste Saleil1-0/+1
This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp instructions in the PowerPC backend. These instructions allow loading and storing VSX register pairs. This patch also adds the VSRp register class definition needed for these instructions. Differential Revision: https://reviews.llvm.org/D84359
2020-09-18[TableGen][GlobalISel] Fix handling of zero_regGabriel Hjort Åkerlund1-0/+5
When generating matching tables for GlobalISel, TableGen would output "::zero_reg" whenever encountering the zero_reg, which in turn would result in compilation error. This patch fixes that by instead outputting NoRegister (== 0), which is the same result that TableGen produces when generating matching tables for ISelDAG. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D86215
2020-08-27[IR] Add NoUndef attribute to Intrinsics.tdJuneyoung Lee1-0/+3
This patch adds NoUndef to Intrinsics.td. The attribute is attached to llvm.assume's operand, because llvm.assume(undef) is UB. It is attached to pointer operands of several memory accessing intrinsics as well. This change makes ValueTracking::getGuaranteedNonPoisonOps' intrinsic check unnecessary, so it is removed. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D86576
2020-08-26Reland [IR] Intrinsics default attributes and opt-out flagsstefan11-65/+90
Intrinsic properties can now be set to default and applied to all intrinsics. If the attributes are not needed, the user can opt-out by setting the DisableDefaultAttributes flag to true. Differential Revision: https://reviews.llvm.org/D70365
2020-08-20Revert "[IR] Intrinsics default attributes and opt-out flag"Johannes Doerfert1-82/+62
This commit introduced a non-trivial compile time regression that needs to be addressed: https://reviews.llvm.org/D70365#2227627 Given that it is unclear how long that will take, I'll revert it for now. This reverts commit eedf18fc1f5fc71bb896204abf41fc5a2dbf25f7.
2020-08-19[IR] Intrinsics default attributes and opt-out flagsstefan11-62/+82
Intrinsic properties can now be set to default and applied to all intrinsics. If the attributes are not needed, the user can opt-out by setting the DisableDefaultAttributes flag to true. Differential Revision: https://reviews.llvm.org/D70365
2020-07-01[MVT] Add new MVT types for RISC-V vector.Hsiangkai Wang1-0/+7
In RISC-V vector extension, users could group multiple vector registers as one pseudo register. In mixed width operations, users could use partial vector registers to reduce the register pressure. The parameter to control register grouping and partial use is called LMUL. LMUL is a part of the type. So, we have a bunch of vector types. In order to support all these types, we need new MVT types in LLVM. In this patch, I added several MVT types that are used in RISC-V vector implementation. This is a standalone patch for MVT types without RISC-V related implementation. Differential revision: https://reviews.llvm.org/D81724
2020-06-30[IR] NoFree IntrinsicProperty.sstefan11-0/+3
Summary: Separate introduction of IntrNoFree property as suggested in D70365 Reviewers: arsenm, nhaehnle Tags: #llvm Differential Revision: https://reviews.llvm.org/D82587
2020-06-25[MVT] Add missing floating point types for 1024/2048-bit vectors.Paul Walker1-0/+5
Summary: This patch adds entries for: v64f16 v128f16 v64bf16 v128bf16 v32f64 Subscribers: dschuff, hiraditya, aheejin, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D82466
2020-05-27Enable `align <n>` to be used in the intrinsic definition.Michael Liao1-8/+12
- This allow us to specify the (minimal) alignment on an intrinsic's arguments and, more importantly, the return value. Differential Revision: https://reviews.llvm.org/D80422
2020-05-27Refactor argument attribute specification in intrinsic definition. NFC.Michael Liao1-8/+9
- Argument attribute needs specifiying through `ArgIndex<n>` (corresponding to `FirstArgIndex`) to distinguish explicitly from the index number from the overloaded type list. - In addition, `RetIndex` (corresponding to `ReturnIndex`) and `FuncIndex` (corresponding to `FunctionIndex`) are introduced for us to associate attributes on the return value and potentially function itself. Differential Revision: https://reviews.llvm.org/D80422
2020-05-27[CodeGen][BFloat] Add bfloat MVT typeTies Stuij1-0/+10
Summary: This patch adds BFloat MVT support. It also adds fixed and scalable vector MVT types for BFloat. This patch is part of a series that adds support for the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile Reviewers: aemerson, huntergr, craig.topper, fpetrogalli, sdesmalen, LukeGeeson, ostannard Reviewed By: ostannard Subscribers: LukeGeeson, pbarrio, dschuff, kristof.beyls, hiraditya, aheejin, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79706
2020-05-14Add v16f64 value typeStanislav Mekhanoshin1-0/+1
We need to use it to handle <16 x double> indirect indexes in the AMDGPU BE. The only visible change from adding it is in ARM cost model. To me it looks reasonable. With doubling a vector size it quadruples the cost up to the size 8 and then it did only double it. Now it also quadruples, which seems a logical progression to me. Actual AMDGPU code is to follow, this is a common part, plus load/store legalization in the AMDGPU BE not to break what works now. Differential Revision: https://reviews.llvm.org/D79952
2020-03-19[VP,Integer,#1] Vector-predicated integer intrinsicsSimon Moll1-2/+4
Summary: This patch adds IR intrinsics for vector-predicated integer arithmetic. It is subpatch #1 of the [integer slice](https://reviews.llvm.org/D57504#1732277) of [LLVM-VP](https://reviews.llvm.org/D57504). LLVM-VP is a larger effort to bring native vector predication to LLVM. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D69891
2020-01-28Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer1-8/+9
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2020-01-09TableGen/GlobalISel: Fix pattern matching of immarg literalsMatt Arsenault1-0/+6
For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-06[NFC] Fix trivial typos in commentsJames Henderson1-2/+2
Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D72143 Patch by Kazuaki Ishizaki.
2019-12-11[TableGen] Remove unused target intrinsic generation logicReid Kleckner1-7/+4
AMDGPU was the last in tree target to use this tablegen mode. I plan to split up the global intrinsic enum similar to the way that clang diagnostics are split up today. I don't plan to build on this mode. Reviewers: arsenm, echristo, efriedma Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D71318
2019-09-19[TableGen] Support encoding per-HwModeJames Molloy1-1/+2
Much like ValueTypeByHwMode/RegInfoByHwMode, this patch allows targets to modify an instruction's encoding based on HwMode. When the EncodingInfos field is non-empty the Inst and Size fields of the Instruction are ignored and taken from EncodingInfos instead. As part of this promote getHwMode() from TargetSubtargetInfo to MCSubtargetInfo. This is NFC for all existing targets - new code is generated only if targets use EncodingByHwMode. llvm-svn: 372320
2019-08-30[ValueTypes] Add v16f16 and v32f16 to EVT::getEVTString and Tablegen's ↵Craig Topper1-0/+2
getEnumName Missed these when I hadded the enum entries llvm-svn: 370494
2019-08-28Add tie-breaker for register class sorting in getSuperRegForSubRegJessica Paquette1-1/+8
llvm::stable_sort is apparently not sufficient. Use the same tie-breaker/sorting style as TopoOrderRC fix bot failures. E.g. http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19401/steps/test-check-all/logs/stdio llvm-svn: 370267
2019-08-27Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette1-0/+40
I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27Revert "[GlobalISel] Import patterns containing INSERT_SUBREG"Jessica Paquette1-40/+0
When EXPENSIVE_CHECKS are enabled, GlobalISelEmitterSubreg.td doesn't get stable output. Reverting while I debug it. See: https://reviews.llvm.org/D66498 llvm-svn: 370080
2019-08-26[GlobalISel] Import patterns containing INSERT_SUBREGJessica Paquette1-0/+40
This teaches the importer to handle INSERT_SUBREG instructions. We were missing patterns involving INSERT_SUBREG in AArch64. It appears in AArch64InstrInfo.td 107 times, and 14 times in AArch64InstrFormats.td. To meaningfully import it, the GlobalISelEmitter needs to know how to infer a super register class for a given register class. This patch introduces the following: - `getSuperRegForSubReg`, a function which finds the largest register class which supports a value type and subregister index - `inferSuperRegisterClass`, a function which finds the appropriate super register class for an INSERT_SUBREG' - `inferRegClassFromPattern`, a function which allows for some trivial lookthrough into instructions - `getRegClassFromLeaf`, a helper function which returns the register class for a leaf `TreePatternNode` - Support for subregister index operands in `importExplicitUseRenderer` It also - Updates tests in each backend which are impacted by the change - Adds GlobalISelEmitterSubreg.td to test that we import and skip the expected patterns As a result of this patch, INSERT_SUBREG patterns in X86 may use the LOW32_ADDR_ACCESS_RBP register class instead of GR32. This is correct, since the register class contains the same registers as GR32 (except with the addition of RBP). So, this also teaches X86 to handle that register class. This is in line with X86ISelLowering, which treats this as a GR class. Differential Revision: https://reviews.llvm.org/D66498 llvm-svn: 369973
2019-08-20Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operandsJessica Paquette1-0/+7
Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
2019-08-15MVT: Add v3i16/v3f16 vectorsMatt Arsenault1-0/+2
AMDGPU has some buffer intrinsics which theoretically could use this. Some of the generated tables include the 3 and 4 element vector versions of these rounded to 64-bits, which is ambiguous. Add these to help the table disambiguate these. Assertion change is for the path odd sized vectors now take for R600. v3i16 is widened to v4i16, which then needs to be promoted to v4i32. llvm-svn: 369038
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-3/+3
Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
2019-08-14[Intrinsics] Add a 'NoAlias' intrinsic property; annotate llvm.memcpyDavid Bolvansky1-0/+3
Reviewers: jdoerfert Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D66158 llvm-svn: 368810
2019-07-17[Attributor] Deduce "willreturn" function attributeHideto Ueno1-0/+3
Summary: Deduce the "willreturn" attribute for functions. For now, intrinsics are not willreturn. More annotation will be done in another patch. Reviewers: jdoerfert Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63046 llvm-svn: 366335
2019-07-15[WebAssembly] Rename except_ref type to exnrefHeejin Ahn1-1/+1
Summary: We agreed to rename `except_ref` to `exnref` for consistency with other reference types in https://github.com/WebAssembly/exception-handling/issues/79. This also renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order to use the file for other reference types in future. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64703 llvm-svn: 366145
2019-07-07[CodeGen] Add larger vector types for i32 and f32David Majnemer1-0/+12
Some out of tree backend require larger vector type. Since maintaining the changes out of tree is difficult due to the many manual changes needed when adding a new type we are adding it even if no backend currently use it. Differential Revision: https://reviews.llvm.org/D64141 Patch by Thomas Raoux! llvm-svn: 365274
2019-06-13[IntrinsicEmitter] Extend argument overloading with forward references.Sander de Smalen1-12/+23
Extend the mechanism to overload intrinsic arguments by using either backward or forward references to the overloadable arguments. In for example: def int_something : Intrinsic<[LLVMPointerToElt<0>], [llvm_anyvector_ty], []>; LLVMPointerToElt<0> is a forward reference to the overloadable operand of type 'llvm_anyvector_ty' and would allow intrinsics such as: declare i32* @llvm.something.v4i32(<4 x i32>); declare i64* @llvm.something.v2i64(<2 x i64>); where the result pointer type is deduced from the element type of the first argument. If the returned pointer is not a pointer to the element type, LLVM will give an error: Intrinsic has incorrect return type! i64* (<4 x i32>)* @llvm.something.v4i32 Reviewers: RKSimon, arsenm, rnk, greened Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62995 llvm-svn: 363233
2019-03-17[CodeGen] Defined MVTs v3i32, v3f32, v5i32, v5f32Tim Renouf1-0/+4
AMDGPU would like to use these MVTs. Differential Revision: https://reviews.llvm.org/D58901 Change-Id: I6125fea810d7cc62a4b4de3d9904255a1233ae4e llvm-svn: 356351
2019-03-12IR: Add immarg attributeMatt Arsenault1-0/+3
This indicates an intrinsic parameter is required to be a constant, and should not be replaced with a non-constant value. Add the attribute to all AMDGPU and generic intrinsics that comments indicate it should apply to. I scanned other target intrinsics, but I don't see any obvious comments indicating which arguments are intended to be only immediates. This breaks one questionable testcase for the autoupgrade. I'm unclear on whether the autoupgrade is supposed to really handle declarations which were never valid. The verifier fails because the attributes now refer to a parameter past the end of the argument list. llvm-svn: 355981
2019-02-12[tablegen] Add locations to many PrintFatalError() callsDaniel Sanders1-10/+18
Summary: While working on the GISel Combiner, I noticed I was producing location-less error messages fairly often and set about fixing this. In the process, I noticed quite a few places elsewhere in TableGen that also neglected to include a relevant location. This patch adds locations to errors that relate to a specific record (or a field within it) and also have easy access to the relevant location. This is particularly useful when multiclasses are involved as many of these errors refer to the full name of a record and it's difficult to guess which substring is grep-able. Unfortunately, tablegen currently only supports Record granularity so it's not currently possible to point at a specific Init so these sometimes point at the record that caused the error rather than the precise origin of the error. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, nhaehnle Reviewed By: nhaehnle Subscribers: jdoerfert, nhaehnle, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58077 llvm-svn: 353862
2019-02-11[tblgen] Add a timer covering the time spent reading the Instruction defsDaniel Sanders1-0/+4
This patch adds a -time-regions option to tablegen that can enable timers (currently only one) that assess the performance of tablegen itself. This can be useful for identifying scaling problems with tablegen backends. This particular timer has allowed me to ignore time that is not attributed the GISel combiner pass. It's useful by itself but it is particularly useful in combination with https://reviews.llvm.org/D52954 which causes this period of time to be annotated within Xcode Instruments which in turn allows profile samples and recorded allocations attributed to reading instructions to be filtered out. llvm-svn: 353763
2019-01-23[IR] Match intrinsic parameter by scalar/vectorwidthSimon Pilgrim1-1/+1
This patch replaces the existing LLVMVectorSameWidth matcher with LLVMScalarOrSameVectorWidth. The matching args must be either scalars or vectors with the same number of elements, but in either case the scalar/element type can differ, specified by LLVMScalarOrSameVectorWidth. I've updated the _overflow intrinsics to demonstrate this - allowing it to return a i1 or <N x i1> overflow result, matching the scalar/vectorwidth of the other (add/sub/mul) result type. The masked load/store/gather/scatter intrinsics have also been updated to use this, although as we specify the reference type to be llvm_anyvector_ty we guarantee the mask will be <N x i1> so no change in behaviour Differential Revision: https://reviews.llvm.org/D57090 llvm-svn: 351957
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-11-14Mark @llvm.trap coldVedant Kumar1-0/+3
A call to @llvm.trap can be expected to be cold (i.e. unlikely to be reached in a normal program execution). Outlining paths which unconditionally trap is an important memory saving. As the hot/cold splitting pass (imho) should not treat all noreturn calls as cold, explicitly mark @llvm.trap cold so that it can be outlined. Split out of https://reviews.llvm.org/D54244. Differential Revision: https://reviews.llvm.org/D54329 llvm-svn: 346885
2018-10-25[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.Clement Courbet1-1/+0
Summary: The pfm counters are now in the ExegesisTarget rather than the MCSchedModel (PR39165). This also compresses the pfm counter tables (PR37068). Reviewers: RKSimon, gchatelet Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D52932 llvm-svn: 345243
2018-09-27llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song1-5/+5
Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
2018-05-23[GlobalISel][Tablegen] Assign small opcodes to pseudosRoman Tereshin1-7/+12
Sort pseudo instructions first while emitting enum's for target instructions info. That puts them close to each other and to generic G_* opcodes for GlobalISel. This makes it easier to build small jump tables over opcodes that could be directly embedded into MatchTable's Tablegen'erated for GlobalISel's InstructionSelect. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D47240 llvm-svn: 333135
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