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path: root/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
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2020-02-19TableGen: Fix logic for default operandsMatt Arsenault1-5/+9
This was checking for default operands in the current DAG instruction, rather than the correct result operand list. I'm not entirly sure how this managed to work before, but was failing for me when multiple default operands were overridden.
2020-02-17[TableGen] Don't elide bitconverts in PatFrag fragments.Simon Tatham1-0/+7
Summary: In the DAG pattern backend, `SimplifyTree` simplifies a pattern by removing bitconverts between two identical types. But that function is also run on the fragments list in instances of `PatFrags`, in which the types haven't been specified yet. So the input and output of the bitconvert always evaluate to the empty set of types, which makes them compare equal. So the test always passes, and bitconverts are unconditionally removed from the PatFrag RHS. Fixed by spotting the empty type set and using it to inhibit the optimization. Reviewers: nhaehnle, hfinkel Reviewed By: nhaehnle Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74627
2020-01-29Fix a couple more implicit conversions that Clang doesn't diagnose.Benjamin Kramer1-1/+2
2020-01-28Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer1-6/+9
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2019-12-30TableGen: Fix assert on PatFrags with predicate codeMatt Arsenault1-5/+21
This assumed a single pattern if there was a predicate. Relax this a bit, and allow multiple patterns as long as they have the same class. This was only broken for the DAG path. GlobalISel seems to have handled this correctly already.
2019-12-22[TableGen] Fixes -Wrange-loop-analysis warningsMark de Wever1-2/+2
This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall. Differential Revision: https://reviews.llvm.org/D71807
2019-12-11[TableGen] Remove unused target intrinsic generation logicReid Kleckner1-2/+1
AMDGPU was the last in tree target to use this tablegen mode. I plan to split up the global intrinsic enum similar to the way that clang diagnostics are split up today. I don't plan to build on this mode. Reviewers: arsenm, echristo, efriedma Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D71318
2019-11-18[SVE][CodeGen] Scalable vector MVT size queriesGraham Hunter1-12/+23
* Implements scalable size queries for MVTs, split out from D53137. * Contains a fix for FindMemType to avoid using scalable vector type to contain non-scalable types. * Explicit casts for several places where implicit integer sign changes or promotion from 32 to 64 bits caused problems. * CodeGenDAGPatterns will treat scalable and non-scalable vector types as different. Reviewers: greened, cameron.mcinally, sdesmalen, rovka Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D66871
2019-11-02Stop static analyzer warnings about using bitwise operators on booleans. NFCI.Simon Pilgrim1-6/+6
Call each of the rebase_if() calls separately.
2019-11-02Revert "[Codegen] Both sides of '&&' are same; fixed"Dávid Bolvanský1-1/+1
This reverts commit edb42dccfafb2c0d25d19175c49d016a7c2e0b13. Buildbot timeouts.
2019-11-02[Codegen] Both sides of '&&' are same; fixedDávid Bolvanský1-1/+1
Summary: Found by PVS Studio Not familiar with this code; no testcase. Reviewers: craig.topper, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69741
2019-09-22[X86][TableGen] Allow timm to appear in output patterns. Use it to remove ↵Craig Topper1-0/+1
ConvertToTarget opcodes from the X86 isel table. We're now using a lot more TargetConstant nodes in SelectionDAG. But we were still telling isel to convert some of them to TargetConstants even though they already are. This is because isel emits a conversion anytime the output pattern has a an 'imm'. I guess for patterns in instructions we take the 'timm' from the 'set' pattern, but for Pat patterns with explcicit output we previously had to say 'imm' since 'timm' wasn't allowed in outputs. llvm-svn: 372525
2019-09-17[SVE][MVT] Fixed-length vector MVT rangesGraham Hunter1-2/+8
* Reordered MVT simple types to group scalable vector types together. * New range functions in MachineValueType.h to only iterate over the fixed-length int/fp vector types. * Stopped backends which don't support scalable vector types from iterating over scalable types. Reviewers: sdesmalen, greened Reviewed By: greened Differential Revision: https://reviews.llvm.org/D66339 llvm-svn: 372099
2019-09-09AMDGPU: Remove code address space predicatesMatt Arsenault1-0/+1
Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due to not be reported as legal. llvm-svn: 371413
2019-08-22Retire llvm::less/equal in favor of C++14 std::less<>/equal_to<>.Benjamin Kramer1-1/+1
llvm-svn: 369674
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere1-1/+1
Now that we've moved to C++14, we no longer need the llvm::make_unique implementation from STLExtras.h. This patch is a mechanical replacement of (hopefully) all the llvm::make_unique instances across the monorepo. llvm-svn: 369013
2019-07-31TableGen: Add MinAlignment predicateMatt Arsenault1-2/+18
AMDGPU uses some custom code predicates for testing alignments. I'm still having trouble comprehending the behavior of predicate bits in the PatFrag hierarchy. Any attempt to abstract these properties unexpectdly fails to apply them. llvm-svn: 367373
2019-07-30AMDGPU: Avoid emitting "true" predicatesMatt Arsenault1-2/+4
Empty condition strings are considerde always true. This removes a lot of clutter from the generated matcher tables. This shrinks the source size of AMDGPUGenDAGISel.inc from 7.3M to 6.1M. llvm-svn: 367326
2019-07-17[TableGen] Do not set ReadNone attribute on intrinsics with side effectsMomchil Velikov1-1/+1
If an intrinsic is defined without outputs, but having side effects, it still can be removed completely from the program. This patch makes TableGen not set Attribute::ReadNone for intrinsics which are declared with IntrHasSideEffects. Differential Revision: https://reviews.llvm.org/D64414 llvm-svn: 366312
2019-07-15TableGen: Add address space to matchersMatt Arsenault1-3/+31
Currently AMDGPU uses a CodePatPred to check address spaces from the MachineMemOperand. Introduce a new first class property so that the existing patterns can be easily modified to uses the new generated predicate, which will also be handled for GlobalISel. I would prefer these to match against the pointer type of the instruction, but that would be difficult to get working with SelectionDAG compatbility. This is much easier for now and will avoid a painful tablegen rewrite for all the loads and stores. I'm also not sure if there's a better way to encode multiple address spaces in the table, rather than putting the number to expect. llvm-svn: 366128
2019-07-04[TableGen] Allow DAG isel patterns to override default operands.Simon Tatham1-6/+20
When a Tablegen instruction description uses `OperandWithDefaultOps`, isel patterns for that instruction don't have to fill in the default value for the operand in question. But the flip side is that they actually //can't// override the defaults even if they want to. This will be very inconvenient for the Arm backend, when we start wanting to write isel patterns that generate the many MVE predicated vector instructions, in the form with predication actually enabled. So this small Tablegen fix makes it possible to write an isel pattern either with or without values for a defaulted operand, and have the default values filled in only if they are not overridden. If all the defaulted operands come at the end of the instruction's operand list, there's a natural way to match them up to the arguments supplied in the pattern: consume pattern arguments until you run out, then fill in any missing instruction operands with their default values. But if defaulted and non-defaulted operands are interleaved, it's less clear what to do. This does happen in existing targets (the first example I came across was KILLGT, in the AMDGPU/R600 backend), and of course they expect the previous behaviour (that the default for those operands is used and a pattern argument is not consumed), so for backwards compatibility I've stuck with that. Reviewers: nhaehnle, hfinkel, dmgreen Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63814 llvm-svn: 365114
2019-05-30[TableGen] New default operand "undef_tied_input"Sjoerd Meijer1-1/+1
This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-20[TableGen] - Type comparison LE should be LT or equal.Pete Couperus1-11/+3
Differential Revision: https://reviews.llvm.org/D61705 llvm-svn: 361183
2019-05-07Revert "[TableGen] Fix a typo"Krasimir Georgiev1-1/+1
Summary: This reverts commit r360106. The revisioin causes llvm-tblgen to hang while generating info for RISCV.td. The root cause might be in the RISCV.td definition but I don't know enough about this to investigate further. Command that starts hangning after r360106: `llvm-build/bin/llvm-tblgen -I llvm/include -I llvm/tools/clang/include -I llvm/lib/Target/RISCV -gen-instr-info llvm/lib/Target/RISCV/RISCV.td` Reviewers: sammccall, yan_luo, craig.topper, gribozavr Reviewed By: gribozavr Subscribers: PkmX, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61632 llvm-svn: 360136
2019-05-07[TableGen] Fix a typoYan Luo1-1/+1
Check "Big" instead of "Small" in the second condition. Differential Revision: https://reviews.llvm.org/D61605 llvm-svn: 360106
2019-03-10Recommit r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers ↵Craig Topper1-1/+15
for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." Includes a fix to emit a CheckOpcode for build_vector when immAllZerosV/immAllOnesV is used as a pattern root. This means it can't be used to look through bitcasts when used as a root, but that's probably ok. This extra CheckOpcode will ensure that the first match in the isel table will be a SwitchOpcode which is needed by the caching optimization in the ISel Matcher. Original commit message: Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355784
2019-03-05Revert r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers for ↵Craig Topper1-15/+1
immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." This caused the first matcher in the isel table for many targets to Opc_Scope instead of Opc_SwitchOpcode. This leads to a significant increase in isel match failures. llvm-svn: 355433
2019-03-01[TableGen][SelectionDAG][X86] Add specific isel matchers for ↵Craig Topper1-1/+15
immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary. Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355224
2019-02-20Add support for pointer types in patternsTom Stellard1-1/+7
Summary: This adds support for defining patterns for global isel using pointer types, for example: def : Pat<(load GPR32:$src), (p1 (LOAD GPR32:$src))>; DAGISelEmitter will ignore the pointer information and treat these types as integers with the same bit-width as the pointer type. Reviewers: dsanders, rtereshin, arsenm Reviewed By: arsenm Subscribers: Petar.Avramovic, wdng, rovka, kristof.beyls, jfb, volkan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57065 llvm-svn: 354510
2019-02-12[tablegen] Add locations to many PrintFatalError() callsDaniel Sanders1-1/+2
Summary: While working on the GISel Combiner, I noticed I was producing location-less error messages fairly often and set about fixing this. In the process, I noticed quite a few places elsewhere in TableGen that also neglected to include a relevant location. This patch adds locations to errors that relate to a specific record (or a field within it) and also have easy access to the relevant location. This is particularly useful when multiclasses are involved as many of these errors refer to the full name of a record and it's difficult to guess which substring is grep-able. Unfortunately, tablegen currently only supports Record granularity so it's not currently possible to point at a specific Init so these sometimes point at the record that caused the error rather than the precise origin of the error. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, nhaehnle Reviewed By: nhaehnle Subscribers: jdoerfert, nhaehnle, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58077 llvm-svn: 353862
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-12-05[TableGen] Preserve order of output operands in DAGISelMatcherGenCraig Topper1-10/+30
Summary: This fixes support in DAGISelMatcher backend for DAG nodes with multiple result values. Previously the order of results in selected DAG nodes always matched the order of results in ISel patterns. After the change the order of results matches the order of operands in OutOperandList instead. For example, given this definition from the attached test case: def INSTR : Instruction { let OutOperandList = (outs GPR:$r1, GPR:$r0); let InOperandList = (ins GPR:$t0, GPR:$t1); let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))]; } the DAGISelMatcher backend currently produces a matcher that creates INSTR nodes with the first result `$r0` and the second result `$r1`, contrary to the order in the OutOperandList. The order of operands in OutOperandList does not matter at all, which is unexpected (and unfortunate) because the order of results of a DAG node does matters, perhaps a lot. With this change, if the order in OutOperandList does not match the order in Pattern, DAGISelMatcherGen emits CompleteMatch opcodes with the order of results taken from OutOperandList. Backend writers can use it to express result reorderings in TableGen. If the order in OutOperandList matches the order in Pattern, the result of DAGISelMatcherGen is unaffected. Patch by Eugene Sharygin Reviewers: andreadb, bjope, hfinkel, RKSimon, craig.topper Reviewed By: craig.topper Subscribers: nhaehnle, craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D55055 llvm-svn: 348326
2018-11-30TableGen/ISel: Allow PatFrag predicate code to access captured operandsNicolai Haehnle1-20/+54
Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
2018-10-08TableGen/CodeGenDAGPatterns: addPredicateFn only onceNicolai Haehnle1-7/+0
Summary: The predicate function is added in InlinePatternFragments, no need to do it here. As a result, all uses of addPredicateFn are located in InlinePatternFragments. Test confirmed that there are no changes to generated files when building all (non-experimental) targets. Change-Id: I720e42e045ca596eb0aa339fb61adf6fe71034d5 Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D51993 llvm-svn: 343977
2018-09-27llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song1-2/+2
Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
2018-09-19[TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::set() where ↵Simon Pilgrim1-3/+3
possible. NFCI. In these cases we are always setting to true. llvm-svn: 342543
2018-09-19[TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::push_back()Simon Pilgrim1-2/+1
As mentioned on D52236, this saves 10secs in debug builds of x86 -gen-dag-isel llvm-svn: 342536
2018-09-18Use pass-by-reference for-range loop. NFCI.Simon Pilgrim1-2/+3
llvm-svn: 342481
2018-09-18Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim1-1/+1
llvm-svn: 342469
2018-09-18[TableGen] CodeGenDAGPatterns::GenerateVariants - full caching of matching ↵Simon Pilgrim1-11/+49
predicates Further extension to D51035, this patch avoids all repeated predicates[] matching by caching as it collects the patterns that have multiple variants. Saves around 25secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D51839 llvm-svn: 342467
2018-08-29Remove debug code accidently committed in rL340837. NFCI.Simon Pilgrim1-3/+0
llvm-svn: 340908
2018-08-28[TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching ↵Simon Pilgrim1-2/+14
predicates CodeGenDAGPatterns::GenerateVariants is a costly function in many tblgen commands (33.87% of the total runtime of x86 -gen-dag-isel), and due to the O(N^2) nature of the function, there are a high number of repeated comparisons of the pattern's vector<Predicate>. This initial patch at least avoids repeating these comparisons for every Variant in a pattern. I began investigating caching all the matches before entering the loop but hit issues with how best to store the data and how to update the cache as patterns were added. Saves around 15secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D51035 llvm-svn: 340837
2018-08-17[TableGen] TypeInfer - Cache the legal types as TypeSetByHwModeSimon Pilgrim1-15/+10
We were just caching the MVT set of legal types, then every call creating a new TypeSetByHwMode with it and passing it back on the stack. There's no need to do this - we can create and cache the whole TypeSetByHwMode once and return a const reference to it each time. Additionally, TypeInfer::expandOverloads wasn't making use of the fact that the cache just contains a default mode containing all the types. Saves up to 30secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50903 llvm-svn: 340042
2018-08-17[TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI.Simon Pilgrim1-3/+10
Avoids repeated count()/find() calls that we've already have the default values for. llvm-svn: 340020
2018-08-16[TableGen] TypeSetByHwMode::operator== optimizationSimon Pilgrim1-8/+10
This operator is called a great deal, by checking for the cheap isSimple equality cases first (a common occurrence) we can improve performance as we avoid a lot of std::map find/iteration in hasDefault. isSimple also means that a default value is present, so we can avoid some hasDefault calls. This also avoids a rather dodgy piece of logic that was checking for isSimple() && !VTS.isSimple() but not the inverse - it now uses the general hasDefault mode comparison test instead. Saves around 15secs in debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50841 llvm-svn: 339890
2018-08-16[TableGen] Avoid self getPredicates() != comparison. NFCI.Simon Pilgrim1-2/+2
We were performing a completely unnecessary full comparison of the same std::vector<Predicate>. llvm-svn: 339888
2018-08-15[TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> ↵Simon Pilgrim1-1/+1
TypeSetByHwMode conversions in getPatternSize I noticed this during profiling of tablegen (PR28222) that we were calling Child->getType(0) which creates a ValueTypeByHwMode on the fly from the requested internal TypeSetByHwMode type and returns it by value, we then treat it as a TypeSetByHwMode reference which involves constructing a new TypeSetByHwMode on the stack with a large amount of std::map iterating/copying all along the way. I am not an expert on tablegen, but AFAICT this is all unnecessary and we should be calling Child->getExtType(0) which returns the original TypeSetByHwMode by reference. This gives me a 90sec reduction in msvc debug builds of x86 -gen-dag-isel. Differential Revision: https://reviews.llvm.org/D50789 llvm-svn: 339812
2018-08-01Fix build bot after r338521Ulrich Weigand1-1/+1
llvm-svn: 338522
2018-08-01[SystemZ, TableGen] Fix shift count handlingUlrich Weigand1-24/+20
The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
2018-07-15[TableGen] std::move vectors into TreePatternNode.Craig Topper1-8/+9
llvm-svn: 337121
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