| Age | Commit message (Collapse) | Author | Files | Lines |
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According to the Apple Silicon Optimization Guide, these are 8.4 with
all features of 8.5 except BTI.
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Cortex-R52+ is an Armv8-R AArch32 CPU.
Technical Reference Manual for Cortex-R52+:
https://developer.arm.com/documentation/102199/latest/
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Oryon is an ARM V8 AArch64 CPU from Qualcomm.
---------
Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>
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This patch removes FEAT_FPMR from list of available of architecture
features, instead enabling FMPR register by default.
Additionally dependencies between architectural features are added and
fixed.
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Generate TargetParser extension information from tablegen. This includes FMV extension information. FMV only extensions are represented by a separate tablegen class.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
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I'm planning to remove StringRef::equals in favor of
StringRef::operator==.
- StringRef::operator==/!= outnumber StringRef::equals by a factor of
70 under llvm/ in terms of their usage.
- The elimination of StringRef::equals brings StringRef closer to
std::string_view, which has operator== but not equals.
- S == "foo" is more readable than S.equals("foo"), especially for
!Long.Expression.equals("str") vs Long.Expression != "str".
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This was [addressed for AArch64
here](https://github.com/llvm/llvm-project/pull/79004), but the same
applies to ARM.
Move the enablement of neon+fp64 to `-mcpu=cortex-r52`, which optionally
supports these features.
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Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.
Technical Reference Manual for Neoverse-N3:
https://developer.arm.com/documentation/107997/latest/
Technical Reference Manual for Neoverse-V3:
https://developer.arm.com/documentation/107734/latest/
Technical Reference Manual for Neoverse-V3AE:
https://developer.arm.com/documentation/101595/latest/
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When `+sve` is passed in the command line, if the Architecture being
targeted is V8.6A/V9.1A or later, `+f32mm` is also added. This enables
FEAT_32MM, however at the time of writing no CPU's support this. This
leads to the FEAT_32MM instructions being compiled for CPU's that do not
support them.
This commit removes the automatic enablement, however the option is
still able to be used by passing `+f32mm`.
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[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs
Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.
Technical Reference Manual for Cortex-A520AE:
https://developer.arm.com/documentation/107726/latest/
Technical Reference Manual for Cortex-A720AE:
https://developer.arm.com/documentation/102828/latest/
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Add support for Arm Cortex A78AE CPU
Technical Reference Manual for Arm Cortex A78AE:
https://developer.arm.com/documentation/101779/0003
Fixes #84450
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This is something we generally tend to avoid due to it confusing the git
history, but with the new github formatting bots being more noisy we
keep running into issues with the existing formatting when adding or
adjusting CPUs. This patch formats the code to make sure we are in a
good state going forward.
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Correct an issue with Arm Neoverse N2 after it was
changed to a v9a core in change
f576cbe44eabb8a5ac0af817424a0d1e7c8fbf85:
* FEAT_FHM should be enabled for this core.
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This reverts commit 89c1bf1230e011f2f0e43554c278205fa1819de5.
This has been unimplemenented for a while, and GCC does not implement
it, therefore we need to consider whether we should just deprecate it
in the ACLE instead.
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This patch changes how the macro __ARM_ARCH is defined to match its
defintion in the ACLE. In ACLE 5.4.1, __ARM_ARCH is defined as equal to
the major architecture version for ISAs up to and including v8. From
v8.1 onwards, its definition is changed to include minor versions, such
that for an architecture vX.Y, __ARM_ARCH = X*100 + Y. Before this
patch, LLVM defined __ARM_ARCH using only the major architecture version
for all architecture versions. This patch adds functionality to define
__ARM_ARCH correctly for architectures greater than or equal to v8.1.
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The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.
Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.
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Before:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/8
...
```
After:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
...
```
Which improves the experience of finding and running this:
```
$ ./unittests/TargetParser/TargetParserTests --gtest_filter=AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
Note: Google Test filter = AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture (0 ms total)
[----------] Global test environment tear-down
[==========] 1 test from 1 test suite ran. (0 ms total)
[ PASSED ] 1 test.
```
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Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.
After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.
The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.
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With a690e86 we added -mcpu/mtune=native support to handle the Microsoft
Azure Cobalt 100 CPU as a Neoverse N2. This patch adds a CPU alias in
TargetParser to maintain compatibility with GCC.
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This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArch64 targets.
Mode details about the Armv9.5-A architecture version can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
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Currently there are several bits of code in the AArch64 driver which
attempt to enforce dependencies between optional features in the -march=
and -mcpu= options. However, these are based on the list of feature
names being enabled/disabled, so they have a lot of logic to consider
the order in which features were turned on and off, which doesn't scale
well as dependency chains get longer.
This patch moves the code handling these dependencies to TargetParser,
and changes them to use a Bitset of enabled features. This makes it easy
to check which features are enabled, and is converted back to a list of
LLVM feature names once all of the command-line options are parsed.
The motivating example for this was the -mcpu=cortex-r82+nofp option.
Previously, the code handling the dependency between the fp16 and
fp16fml extensions did not consider the nofp modifier, so it added
+fullfp16 to the feature list. This should have been disabled by the
+nofp modifier, and also the backend did follow the dependency between
fullfp16 and fp, resulting in fp being turned back on in the backend.
Most of the dependencies added to AArch64TargetParser.h weren't known
about by clang before, I built that list by checking what the backend
thinks the dependencies between SubtargetFeatures are.
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This patch defines AEK_JSCVT and AEK_FCMA for CPU features FEAT_JSCVT
and FEAT_FCMA respectively, and add them to the feature set of TSV110.
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(#76932)
Remove AArch64::AEK_FP16ML from Arm Cortex-A78C definition, as
this is not supported, according to the Technical Reference Manual:
https://developer.arm.com/documentation/102226/latest/
Also add AArch64::AEK_FLAGM (Flag Manipulation) to Arm Cortex-X1C
and Arm Cortex-X2 as these were missing previously, but are
supported, according to the Technical Reference Manuals:
https://developer.arm.com/documentation/101968/latest/
https://developer.arm.com/documentation/101803/latest/
Fixes #62383
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This implements assembly support for the Memory Systems Extensions
introduced as part of the Armv9.5-A architecture version.
The changes include:
* New subtarget feature for FEAT_TLBIW.
* New system registers for FEAT_HDBSS:
* HDBSSBR_EL2 and HDBSSPROD_EL2.
* New system registers for FEAT_HACDBS:
* HACDBSBR_EL2 and HACDBSCONS_EL2.
* New TLBI instructions for FEAT_TLBIW:
* VMALLWS2E1(nXS), VMALLWS2E1IS(nXS) and VMALLWS2E1OS(nXS).
* New system register for FEAT_FGWTE3:
* FGWTE3_EL3.
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This reverts commit 9f0f5587426a4ff24b240018cf8bf3acc3c566ae.
Fix expensive checks failure by properly marking register def for ADR.
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This reverts commit 5992ce90b8c0fac06436c3c86621fbf6d5398ee5.
Builtbot failures with expensive checks enabled.
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- Adds a new +pc option to -mbranch-protection that will enable
the use of PC as a diversifier in PAC branch protection code.
- When +pauth-lr is enabled (-march=armv9.5a+pauth-lr) in combination
with -mbranch-protection=pac-ret+pc, the new 9.5-a instructions
(pacibsppc, retaasppc, etc) are used.
Documentation for the relevant instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
Co-authored-by: Lucas Prates <lucas.prates@arm.com>
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Extension (#73777)
This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>
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This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.
I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
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Neoverse N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so -mcpu=neoverse-n2+crypto is required
to enable crypto for this core.
Neoverse N2 Technical Reference Manual:
https://developer.arm.com/documentation/102099/0003/
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Cortex-M52 is an Armv8.1 AArch32 CPU.
Technical specifications available at:
https://developer.arm.com/processors/cortex-m52
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This is the failure:
https://lab.llvm.org/buildbot/#/builders/236/builds/7728/steps/10/logs/stdio
This started with eef8e1d206dc01c081a0ca29b7f9e0c39d33446e, but because
there were a couple of patches that came after that I had to revert all
3 of them because of merge conflicts.
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This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>
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These are still v8.6a and have no real changes as far as LLVM cares, so
it's mostly just a copy/paste job.
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We pretended they were v8.5a in the past because LLVM's modelling used
to fold SM4 crypto support into v8.6a (which the CPUs don't actually
have). That's changed in the last year so we can use the real value.
This is mostly a tidy-up commit before one that'll bring in A17 and M3.
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Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.
Technical Reference Manual for Cortex-A520:
https://developer.arm.com/documentation/102517/latest/
Technical Reference Manual for Cortex-A720:
https://developer.arm.com/documentation/102530/latest/
Technical Reference Manual for Cortex-X4:
https://developer.arm.com/documentation/102484/latest/
Patch co-authored by: Sivan Shani <sivan.shani@arm.com>
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This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.
Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Patch by Oliver Stannard.
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This patch adds the feature flags of SME_F8F16 and SME_F8F32,
and the assembly/disassembly for the following instructions of SME2:
* SME:
- FMLAL, FMLALL
- FVDOT, FVDOTT
- FVDOTB
- FMOPA
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
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This patch adds the feature flags of LUT and SME_LUTv2, and the
assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON:
- LUT2
- LUT4
* SVE2:
- LUTI2_ZZZI
- LUTI4_ZZZI
- LUTI4_Z2ZZI
* SME:
- MOVT
- LUTI4_4ZZT2Z
- LUTI4_S_4ZZT2Z
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
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This patch adds the feature flag FDOT2/FDOT4 and the
assembly/disassembly
for the following instructions of NEON and SVE2:
* NEON:
- FDOTlane
- FDOT
* SVE2:
- FDOT_ZZZI_BtoH
- FDOT_ZZZ_BtoH
- FDOT_ZZZI_BtoS
- FDOT_ZZZ_BtoS
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
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This patch adds the feature flag FP8FMA and the assembly/disassembly
for the following instructions of NEON and SVE2:
* NEON:
- FMLALBlane
- FMLALTlane
- FMLALLBBlane
- FMLALLBTlane
- FMLALLTBlane
- FMLALLTTlane
- FMLALB
- FMLALT
- FMLALLB
- FMLALLBT
- FMLALLTB
- FMLALLTT
* SVE2:
- FMLALB_ZZZI
- FMLALT_ZZZI
- FMLALB_ZZZ
- FMLALT_ZZZ
- FMLALLBB_ZZZI
- FMLALLBT_ZZZI
- FMLALLTB_ZZZI
- FMLALLTT_ZZZI
- FMLALLBB_ZZZ
- FMLALLBT_ZZZ
- FMLALLTB_ZZZ
- FMLALLTT_ZZZ
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
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…mbly.
This patch adds the feature flag FAMINMAX and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON:
- FAMIN
- FAMAX
* SVE2:
- FAMIN_ZPmZ
- FAMAX_ZPmZ
* SME2:
- FAMAX_2Z2Z
- FAMIN_2Z2Z
- FAMAX_4Z4Z
- FAMIN_4Z4Z
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
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(#69632)
This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON Instructions:
+ Advanced SIMD two-register miscellaneous:
- F1CVTL, F1CVTL2, F2CVTL, F2CVTL2
- BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
+ Advanced SIMD three-register extension:
- FCVTN, FCVTN2 (FP32 to FP8)
- FCVTN (FP16 to FP8)
+ Advanced SIMD three same:
- FSCALE
* SVE2 Instructions:
+ Downconvert instructions:
- FCVTN_Z2Z_HtoB
- FCVTNB_Z2Z_StoB
- BFCVTN_Z2Z_HtoB
- FCVTNT_Z2Z_StoB
+ Upconvert instructions:
- F1CVT_ZZ, F2CVT_ZZ
- BF1CVT_ZZ, BF2CVT_ZZ
- F1CVTLT_ZZ, F2CVTLT_ZZ
- BF1CVTLT_ZZ, BF2CVTLT_ZZ
* SME2 Instructions:
- F1CVT_2ZZ, F2CVT_2ZZ
- BF1CVT_2ZZ, BF2CVT_2ZZ
- F1CVTL_2ZZ, F2CVTL_2ZZ
- BF1CVTL_2ZZ, BF2CVTL_2ZZ
- FCVT_Z2Z_HtoB, BFCVT_Z2Z_HtoB
- FCVT_Z4Z - FCVTN_Z4Z
- FSCALE_2ZZ, FSCALE_4ZZ
- FSCALE_2Z2Z, FSCALE_4Z4Z
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
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Also add Read only registers:
ID_AA64FPFR0_EL1
ID_AA64ISAR3_EL1
This is based on this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
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Enables summary descriptions along with the names of the feature.
Descriptions here are simply looked up via the available llvm tablegen
data.
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```
$ ./bin/clang --target=arm-linux-gnueabihf --print-supported-extensions
<...>
All available -march extensions for ARM
crc
crypto
sha2
aes
dotprod
<...>
```
This follows the format set by RISC-V and AArch64. As for AArch64, ARM
doesn't have versioned extensions like RISC-V does. So there is only 1
column, which contains the name.
Any extension without a "feature" is hidden as these cannot be used with
-march.
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This triggers a lot of -Wctad-maybe-unsupported
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Use Bitset instead of BitMasking for the Architecture Extensions,
as the number of extensions will exceed the bitmask bits eventually.
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