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author | Wei Zhao <60720283+wxz2020@users.noreply.github.com> | 2024-06-06 09:27:50 -0500 |
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committer | GitHub <noreply@github.com> | 2024-06-06 07:27:50 -0700 |
commit | 6b9753a0ecf7fdea203c6faf23c3ad4bf432273c (patch) | |
tree | a4991aa2262db91373713d9e1734f7a29d9d4851 /llvm/unittests/TargetParser/TargetParserTest.cpp | |
parent | 2a6efe6a49e00a1953d537816a39e5c9883dc3c0 (diff) | |
download | llvm-6b9753a0ecf7fdea203c6faf23c3ad4bf432273c.zip llvm-6b9753a0ecf7fdea203c6faf23c3ad4bf432273c.tar.gz llvm-6b9753a0ecf7fdea203c6faf23c3ad4bf432273c.tar.bz2 |
[AArch64] Add support for Qualcomm Oryon processor (#91022)
Oryon is an ARM V8 AArch64 CPU from Qualcomm.
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Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>
Diffstat (limited to 'llvm/unittests/TargetParser/TargetParserTest.cpp')
-rw-r--r-- | llvm/unittests/TargetParser/TargetParserTest.cpp | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 797d7df..571031d 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1815,11 +1815,23 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_RDM}), - "8.2-A")), + "8.2-A"), + ARMCPUTestParams<AArch64::ExtensionBitset>( + "oryon-1", "armv8.6-a", "crypto-neon-fp-armv8", + (AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_PAUTH, + AArch64::AEK_FCMA, AArch64::AEK_JSCVT, AArch64::AEK_SIMD, + AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_SM4, + AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2, + AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_RAND, + AArch64::AEK_PROFILE, AArch64::AEK_CRYPTO})), + "8.6-A")), + ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 76; +static constexpr unsigned NumAArch64CPUArchs = 77; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; |