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path: root/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-2/+2
2016-10-09Move the global variables representing each Target behind accessor functionMehdi Amini1-4/+6
2016-03-09This change adds co-processor condition branching and conditional traps to th...Chris Dewhurst1-0/+47
2016-02-27The patch adds missing registers and instructions to complete all the registe...Chris Dewhurst1-0/+72
2016-02-26Reverting breaking change. Sorry.Chris Dewhurst1-72/+0
2016-02-26Reviewed at reviews.llvm.org/D17133Chris Dewhurst1-0/+72
2016-01-26Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer1-1/+1
2015-10-04[SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger1-0/+15
2015-08-10[Sparc] Implement i64 load/store support for 32-bit sparc.James Y Knight1-0/+37
2015-06-23Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko1-1/+1
2015-06-19Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko1-1/+1
2015-05-18Sparc: Add the "alternate address space" load/store instructions.James Y Knight1-0/+11
2015-05-18Add support for the Sparc implementation-defined "ASR" registers.James Y Knight1-0/+19
2015-05-15Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper1-0/+1
2015-05-13MC: Modernize MCOperand API naming. NFC.Jim Grosbach1-12/+12
2015-04-29[Sparc] Really add sparcel architecture support.Douglas Katzman1-15/+18
2014-11-12Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola1-11/+7
2014-11-10Misc style fixes. NFC.Rafael Espindola1-35/+22
2014-04-29[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper1-6/+6
2014-04-22[Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth1-2/+2
2014-04-15[MC] Require an MCContext when constructing an MCDisassembler.Lang Hames1-8/+5
2014-03-09[Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju1-0/+36
2014-03-02[Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju1-0/+30
2014-03-02[Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju1-0/+36
2014-03-02[Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju1-0/+13
2014-03-01[Sparc] Add support to decode negative simm13 operands in the sparc disassemb...Venkatraman Govindaraju1-0/+9
2014-03-01[Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju1-0/+21
2014-03-01[Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju1-0/+110
2014-01-12[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.Venkatraman Govindaraju1-9/+9
2014-01-06[Sparc] Explicitly cast -1 to unsigned to fix buildbot errors.Venkatraman Govindaraju1-8/+8
2014-01-06[Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju1-0/+228
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