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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-02 21:17:44 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-02 21:17:44 +0000 |
commit | 4fa2ab26f5dca2a038798d76e1760c52e8786b72 (patch) | |
tree | 9d939a8153915287ac3e5b15a506688fd3f40885 /llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | |
parent | 49c8ae21f59608479727cdaafa880e51c5f10e15 (diff) | |
download | llvm-4fa2ab26f5dca2a038798d76e1760c52e8786b72.zip llvm-4fa2ab26f5dca2a038798d76e1760c52e8786b72.tar.gz llvm-4fa2ab26f5dca2a038798d76e1760c52e8786b72.tar.bz2 |
[Sparc] Add support for decoding jmpl/retl/ret instruction.
llvm-svn: 202663
Diffstat (limited to 'llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index e01196c..ea4d6da 100644 --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -207,6 +207,8 @@ static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, + const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -379,3 +381,37 @@ static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, MI.addOperand(MCOperand::CreateImm(tgt)); return MCDisassembler::Success; } + +static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder) { + + unsigned rd = fieldFromInstruction(insn, 25, 5); + unsigned rs1 = fieldFromInstruction(insn, 14, 5); + unsigned isImm = fieldFromInstruction(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); + else + rs2 = fieldFromInstruction(insn, 0, 5); + + // Decode RD. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MI.addOperand(MCOperand::CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + return MCDisassembler::Success; +} |