aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2020-01-23[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON.Simon Tatham1-14/+0
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2020-01-14[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-4/+69
2020-01-11[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song1-13/+7
2020-01-10Reverting, broke some bots. Need further investigation.Diogo Sampaio1-69/+4
2020-01-10[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-4/+69
2019-09-09[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard1-0/+6
2019-07-28[ARM] MVE VPNOTDavid Green1-0/+10
2019-07-23[ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green1-4/+4
2019-07-19[ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev1-0/+7
2019-06-28[ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham1-2/+2
2019-06-27[ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham1-8/+8
2019-06-27[ARM] Make coprocessor number restrictions consistent.Simon Tatham1-8/+1
2019-06-27[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham1-1/+13
2019-06-25[ARM] Add remaining miscellaneous MVE instructions.Simon Tatham1-1/+22
2019-06-25[ARM] Add MVE vector load/store instructions.Simon Tatham1-0/+157
2019-06-24[ARM] Add MVE interleaving load/store family.Simon Tatham1-0/+36
2019-06-21Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim1-1/+1
2019-06-21[ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham1-0/+69
2019-06-21[ARM] Add MVE vector instructions that take a scalar input.Simon Tatham1-0/+29
2019-06-21[ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham1-0/+27
2019-06-21[ARM] Fix -Wimplicit-fallthrough after D62675Fangrui Song1-0/+2
2019-06-21[ARM] Add MVE vector compare instructions.Simon Tatham1-0/+43
2019-06-21[ARM] Add a batch of MVE floating-point instructions.Simon Tatham1-0/+49
2019-06-20[ARM] Add a batch of MVE integer instructions.Simon Tatham1-0/+31
2019-06-20[llvm-objdump] Switch between ARM/Thumb based on mapping symbols.Eli Friedman1-29/+28
2019-06-19[ARM] Add MVE vector bit-operations (register inputs).Simon Tatham1-0/+14
2019-06-18[ARM] Rename MVE instructions in Tablegen for consistency.Simon Tatham1-6/+6
2019-06-13[ARM] Set up infrastructure for MVE vector instructions.Simon Tatham1-26/+265
2019-06-13[ARM] Refactor handling of IT mask operands.Simon Tatham1-9/+16
2019-06-11[ARM] First MVE instructions: scalar shifts.Mikhail Maltsev1-0/+118
2019-06-11[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham1-15/+351
2019-06-11Revert CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-06-10CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-06-10Revert rL362953 and its followup rL362955.Simon Tatham1-351/+15
2019-06-10[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham1-15/+351
2019-05-28[ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham1-2/+2
2019-05-14[ARM] Create a TargetInfo header. NFCRichard Trieu1-0/+1
2019-04-23ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover1-1/+13
2019-03-08[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operandDiogo N. Sampaio1-0/+9
2019-02-25[ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham1-4/+12
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-07-30Remove trailing spaceFangrui Song1-5/+5
2018-06-26ARM: correctly decode VFP instructions following unpredictable t2ITTim Northover1-0/+2
2018-06-26ARM: diagnose unpredictable IT instructionsTim Northover1-1/+4
2018-03-06[ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath1-2/+3
2018-02-08[ARM] Re-commit r324600 with fixed LLVMBuild.txtOliver Stannard1-9/+2
2018-02-08Revert r324600 as it breaks a buildbotOliver Stannard1-2/+9
2018-02-08[ARM] Fix disassembly of invalid banked register movesOliver Stannard1-9/+2
2018-01-26[ARM] Armv8.2-A FP16 code generation (part 1/3)Sjoerd Meijer1-0/+7
generated by cgit v1.1 at 2025-09-30 00:24:51 +0000