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path: root/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
AgeCommit message (Expand)AuthorFilesLines
2016-09-09AMDGPU: Fix immediate folding logic when shrinking instructionsMatt Arsenault1-8/+2
2016-09-08AMDGPU: Try to commute when selecting s_addk_i32/s_mulk_i32Matt Arsenault1-9/+14
2016-09-03AMDGPU: Fix adding duplicate implicit exec usesMatt Arsenault1-1/+15
2016-08-29AMDGPU/SI: Improve register allocation hints for sopk instructionsTom Stellard1-0/+1
2016-07-19AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault1-1/+5
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-2/+2
2016-06-24AMDGPU: Cleanup subtarget handling.Matt Arsenault1-2/+3
2016-06-20AMDGPU: Preserve undef flag on vcc when shrinking v_cndmask_b32Matt Arsenault1-16/+13
2016-06-09AMDGPU: Properly initialize SIShrinkInstructionsMatt Arsenault1-8/+2
2016-04-25Add optimization bisect opt-in calls for AMDGPU passesAndrew Kaylor1-0/+3
2016-04-25AMDGPU/SI: Optimize adjacent s_nop instructionsMatt Arsenault1-0/+27
2016-04-16AMDGPU: Use s_addk_i32 / s_mulk_i32Matt Arsenault1-12/+45
2016-03-11AMDGPU: Materialize sign bits with bfrevMatt Arsenault1-0/+24
2016-03-02AMDGPU: Simplify boolean conditional return statementsMatt Arsenault1-4/+1
2016-02-16[AMDGPU] Rename $dst operand to $vdst for VOP instructions.Tom Stellard1-2/+2
2015-10-20AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault1-2/+1
2015-09-10AMDGPU: Simplify debug printingMatt Arsenault1-1/+1
2015-08-08AMDGPU/SI: Remove VCCRegMatt Arsenault1-2/+11
2015-08-08AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault1-11/+32
2015-07-14AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructionsTom Stellard1-6/+27
2015-07-13AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard1-2/+14
2015-07-09AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one...Tom Stellard1-1/+1
2015-06-13R600 -> AMDGPU renameTom Stellard1-0/+272
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