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author | Tom Stellard <thomas.stellard@amd.com> | 2015-07-14 14:15:03 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2015-07-14 14:15:03 +0000 |
commit | e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2 (patch) | |
tree | 05621cfebec381c7ed8621cd789a6dbaf0ae4ac7 /llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | |
parent | a927a86c72f7715a5a118438eefa442c49c3cff7 (diff) | |
download | llvm-e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2.zip llvm-e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2.tar.gz llvm-e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2.tar.bz2 |
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11061
llvm-svn: 242146
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index e7511e6..5d00bdd6 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -95,13 +95,18 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, // a register allocation hint pre-regalloc and then do the shrining // post-regalloc. if (Src2) { - if (MI.getOpcode() != AMDGPU::V_MAC_F32_e64) - return false; + switch (MI.getOpcode()) { + default: return false; - const MachineOperand *Src2Mod = - TII->getNamedOperand(MI, AMDGPU::OpName::src2_modifiers); - if (!isVGPR(Src2, TRI, MRI) || (Src2Mod && Src2Mod->getImm() != 0)) - return false; + case AMDGPU::V_MAC_F32_e64: + if (!isVGPR(Src2, TRI, MRI) || + TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) + return false; + break; + + case AMDGPU::V_CNDMASK_B32_e64: + break; + } } const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); @@ -250,6 +255,22 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { continue; } + if (Op32 == AMDGPU::V_CNDMASK_B32_e32) { + // We shrink V_CNDMASK_B32_e64 using regalloc hints like we do for VOPC + // instructions. + const MachineOperand *Src2 = + TII->getNamedOperand(MI, AMDGPU::OpName::src2); + if (!Src2->isReg()) + continue; + unsigned SReg = Src2->getReg(); + if (TargetRegisterInfo::isVirtualRegister(SReg)) { + MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); + continue; + } + if (SReg != AMDGPU::VCC) + continue; + } + // We can shrink this instruction DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << '\n';); |